Study On Energy-efficient Capacitor Array DAC For SAR ADC

With the rapid development of low-power electronic terminal equipment,consumer demand for the cruising power of equipment is getting higher and higher,and some even require battery power to maintain more than a few years.Analog-to-digital converter?ADC?is responsible for converting analog signals into digital signals,one of the core modules of electronic terminal equipment,so low-power design is one of the major challenges of ADC design.In a variety of ADC architectures,Successive Approximation?SAR?ADCs are widely used because of their simplicity,less analog modules,smaller area,lower power consumption,and compatibility with digital CMOS processes.SAR ADC is mainly composed of capacitor array DAC,comparator and successive approximation shift register.Some studies show that capacitor array DAC is one of the important sources of ADC energy consumption.Therefore,this paper will focus on energy-efficient capacitor array DAC.The main contents and innovations of the paper are as follows:1.A low complexity capacitor array DAC structure is proposed,four energy-efficient switching schemes for the DAC structure were studied,and based on one of the switching schemes to design a 10-bit low-power SAR ADC.?1?Low complexity capacitance array DAC structure.The capacitor array DAC structure has two characteristics:?1?The lowest bit capacitor using common mode voltage?Vcm?as the reference level,reducing the dependence on the accuracy of V_cm;?2?Each capacitor has only two reference levels,reducing the logic control circuit and The complexity of the capacitor drive circuit.?2?Four energy-efficient DAC switch schemes?111 switch scheme,000 switch scheme,011 switch scheme,100 switch scheme?.111 and 000 switch schemes uses a switching method similar to a monotonic structure switching scheme,except that the LSB capacitor uses a common mode voltage as the reference level.Compared with the 10-bit conventional structure switch scheme,its DAC energy consumption reduced by 90.64%,the number of unit capacitor decreased by 75%.The feature of 100 and 011 switching schemes is that the initial reference level of MSB capacitor is different from other capacitors'.Compared with the 10-bit conventional structure switch scheme,its DAC energy consumption decreased by 95.34%,the number of unit capacitor decreased by 75%.By comparison,the 100 and 011 switching schemes have a good compromise in the energy consumption of the capacitor array,the number of unit capacior,the accuracy,the common mode voltage offset,and the complexity of the logic circuit.?3?10-bit low-power SAR ADC circuit.The SAR ADC is based on a 100-switch scheme.In the circuit design using two full dynamic comparator,successive approximation shift register based on dynamic logic unit and other low-power circuit module.This SAR ADC is designed and simulated in 180 nm CMOS technology.The simulation results show that,when supply voltage is 1 V and sampling rate is 100KS/s,the ADC achieves an ENOB of 9.99 bit,consumes 0.45?W,resulting in a Figure-of-Merit?FOM?of 4.4 fJ/conv.-step.Validated the proposed energy-efficient low-complexity capacitive array DAC switching scheme suitable for the design of low-power SAR ADC.2.Three bit-adjustable energy-efficient capacitor array DAC structure switching scheme are proposed.?1?Capacitor array DAC structure switching scheme based on capacitor combination method.The capacitor array DAC uses top-plate sampling and voltage shifting techniques in the first two comparisons,using charge sharing and voltage monotonic reduction techniques from the third comparison conversion.Compared with the 10-bit conventional structure switching scheme,the DAC energy consumption reduced by 99.22%,the number of unit capacitor reduced by 50%.?2?Capacitor array DAC structure switching scheme based on capacitor multiplexing Method.The structure consists of two sub-arrays in the same structure.During the switching process,the capacitor in the subarray is converted twice by capacitive multiplexing.Compared with the 10-bit conventional structure switching scheme,the DAC energy consumption reduced by 99.89%,the number of unit capacitor reduced by 96.875%.?3?Capacitor array DAC structure switching scheme based on closed-loop charge recyling method.The capacitor array DAC using closed-loop charge recyling method,the switching process does not produce switching energy,each capacitor requires only two reference levels,reducing the difficulty of designing the capacitance drive circuit.Compared with the 10-bit conventional structure switching scheme,its DAC energy consumption?Behavioral energy consumption?reduced by 100%.3.A 8-10 bit-adjustable energy-efficient capacitor array DAC structure switching scheme is proposed,and the 8-10 bit-adjustable SAR ADC circuit is designed based on this scheme.The switching scheme combines the capacitor combining method and the V_cm-based structure switching scheme,the MSB capacitor and the MSB-1 capacitor are connected with the other capacitors through the segment switch to realize the 8-10 bit-adjustable switching energy reduction.Based on this switching scheme,an 8-10 bit-adjustable SAR ADC is designed.The SAR ADC includes a bit control circuit,a two-stage full-dynamic comparator,a successive approximation shift register based on dynamic logic unit and other low-power circuit module.This SAR ADC is designed and simulated in 180 nm CMOS technology.The simulation results show that,when supply voltage is 1 V and sampling rate is 100KS/s,the8-bit ADC achieves an ENOB of 7.98 bit,consumes 0.81?W,resulting in a FOM of 32.08fJ/conv.-step.The 9-bit ADC achieves an ENOB of 8.95 bit,consumes 0.91?W,resulting in a FOM of 18.40 fJ/conv.-step.The 10-bit ADC achieves an ENOB of 9.90 bit,consumes 1.01?W,resulting in a FOM of 10.57 fJ/conv.-step.Validated the proposed 8-10 bit-adjustable energy-efficient capacitor array DAC structure switching scheme can be used for bit-adjustable low-power SAR ADC designs.