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Theoretical And Experimental Study Of Innovative Thin-film Gated SOI Lateral PIN Optoelectronic Device

Posted on:2018-01-24Degree:DoctorType:Dissertation
Country:ChinaCandidate:G L LiFull Text:PDF
GTID:1318330542983727Subject:Circuits and Systems
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Silicon-on-insulator(SOI)lateral P+/P-/N+(PIN)diode has triggered large interests and perspectives for optical sensing,thanks to its demonstrated superior performances such as low leakage current.To extend the optical sensing capability of the SOI lateral PIN diode within the ultraviolet,-visible and near infrared wavelength ranges,improve the optical response and optimize the device electrical and optical performances,this thesis comprehensively and deeply investigates the electrical and optical performance of the SOI lateral PIN diode with additional electrical gate electrode or optical reflector layers.Firstly,an indium-tin-oxide(ITO)top transparent gated SOI lateral PIN diode is theoretically investigated.Based on two-dimensional(2-D)device simulations,the ITO-gated SOI lateral PIN diode highly yields 97%of internal quantum efficiency(QI)and maximizes output photocurrent,under the fully-depleted(FD)condition achieved by the top gate bias.In the experiments,aluminum(Al)backside electrode is implemented with a SOI lateral PIN diode suspended on a micro-hotplate platform.The device measured output photocurrent indeed reaches a maximum,proportional to length of the intrinsic region,under the FD condition achieved by the positive back-gate bias.The electrical performance optimization by the gate bias is analyzed in device numerical simtulation and validated in experimental characterizations in the SOI gated lateral PIN diode.Device degradation is induced(e.g.trap introduction)and observed with regards to the forward and reverse characteristics in the SOI lateral PIN diode on membrane,after the microelectromechanical(MEMS)post-processing(i.e.deep reactive ion etching(DRIE)or aluminum deposition).A low-temperature(?250?)in-situ(i.e.using the embedded micro-heater)annealing of the SOI lateral PIN diode after post-processing is carried out to reduce the diode leakage current,e.g.by about one order of magnitude from 10-12-10-11 A(before annealing)to 10-13-10-12 A(after annealing),to optimize the device optical response(e.g.a maximum increase by?12%of the output photocurrent),and to improve the device low-frequency noise characteristics by neutralizing the interface traps,thereby improving carriers' lifetime and surface recombination velocity.Numerical simulations performed in Atlas/SILVACO for deeper analysis of the leakage current behavior in the lateral PIN diode before and after annealing,show good qualitative agreement with the experimental leakage behavior,providing an in-depth understanding of the phenomena.For the device optical performance,four different backside reflectors(silicon substrate,bottom gold layer,aluminum backside layer and black silicon wafer)are used and placed below the SOI lateral PIN diodes to investigate the optical response(i.e.output photocurrent and responsivity).On the basis of the specific multilayer stacks of the PIN photodiodes with different backside reflectors placed below,2-D device numerical simulations performed in Atlas/SILVACO,identifying varied optical absorption in the lateral PIN photodiodes.Four specific optical signals(photocurrents or responsivities)are obtained under same incident illumination in experiments,due to the varied light absorption into the active Si film.Calibrating the ratios of the four measured photocurrents under same illumination,multiple-wavelength detection has been consequently achieved,without requiring the absolute devices responsivities and the incident optical power density.Moreover,with operation of the micro-hotplate heater,the suspended SOI PIN photodiode can work reliably up to 200? and achieve the improved optical response by bottom mirror,with in-situ temperature sensing and control.Finally,to achieve optical sensing capability within the ultraviolet wavelength range,an innovative ultra-thin SOI lateral PIN diode is experimentally fabricated,with XeF2 thinning,graphene transfer and chip-on-board assembling.Device degradation is not induced by the-fabrication post-processing.In the ultra-thin photodiodes with and without graphene,the optical response(i.e.responsivity)is quite close within the 200-900 nm wavelength range and achieves a maximum responsivity of 0.18 A/W at 390 nm wavelength in the photodiode with maximum intrinsic length 20 ?m.Large improvement of responsivity is also achieved for wavelength below 600 nm,as a result of backside illumination technique.A graphene-gate control has been primarily demonstrated for the optimization of device output optical response.
Keywords/Search Tags:Silicon-on-insulator(SOI), PIN(P+/P-/N+), photodiode, gate control, local anealing, backside reflector, graphene
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