Design And Validation Of 10Gbps True Random Number Generator

Quantum Key Distribution (QKD) system demands real-time true random number.The random number generate data rate of the commercial true random number generator chips is far from the real-time requirements of the QKD system. One way is to use multi chips at a time to serialize the parallel random number bits from multi chips into to a high speed true random number sequence. However, the system become complex and it may not meet the increasing requirements in the future QKD system. Nowadays,some researches develops high-speed true random number generating system, the large system takes large volume and limits its usage in applications.We propose a multi-channel ultra high data rate true random number generator in semiconductor chip. The chip should meet the following requirements:1. The random number output data rate should be up to 1 Gbps per channel. The data rate should be fixed to the request. For each request (clock), the chip should pro-vides a random number bit;2. There should be at least four channels in one single-chip to meet the parallel demands of true random numbers in the quantum light source at a specified frequency;3. Try to control the volume and power consumption for upgrading and integrating of the QKD system.To achieve above, we study a lot.To accomplished the target in a short time, the quantum method is excluded from consider. Although the quantum random number generator can guarantee the quali-ty of the random number for its quantum characteristic, the quantum random number generator usually takes large volume at present. And for the quantum characteristic,the quantum random number generator can not generate at a fixed frequency without a buffer.We study the classical methods for true random number generate and finally fo-cused on the method of the clock jitter in digital circuits. The method can be verified by FPGA and some researches have been reported.During the design with semiconductor CMOS process, we optimized the structure from the previous work and the advantage of the method. The randomness is sampled at ring oscillator which is the beginning of the whole structure. This change can largely improve the max speed of the design, and make it possible to generate 0 Gbps random number at 1 GHz clock input.In the design, we also provide SPI configuration bus to bypass the post-processing module, configure the entropy sources, channel switch and other functions.The design is fabricated in a MPW run, and we assemble design in a QFN package and test the design.Then, the 1 Gbps random data acquired by the high-speed true random number verification system and send to take the NIST statistical test.Finally, we achieved the the chip design with following goals.1. With a 6mmX6mm QFN48 package, the chip integrate ten independent true random number generators which can work at a fixed frequency up to 1 Gbps.2. With 3.3 V IO power supply and 1.2 V core power supply, typical power con-sumption is 800 mW all channel on 1 Gbps data generation rate.3. The true random number generated at 1 Gbps can pass the NIST true random numbers verification.At present, the prototype chip has been delivered to end user for feedback, and there are plans to update to the latest QKD system.The primary innovations of thesis are as follows.1. In the 6mmX6mm QFN48 package, achieveing a 10-channel independent true random number generator, each channel data generation rate is up to 1Gbps, the chip has a high speed and high integration characteristics.2. A complete true random number test platform is established, and the random verification of the chip is realized. The test results show that its randomness can meet the requirements of NIST standard.3. Multi-channel true random number verification system use speed matching data acquisition technology, simplifying the verification work.