Design And Optimization Of Ultra Low Power True Random Number Generator For IOT Application

With the rapid development of the Internet of Things(IOT)technology,the information security of IOT devices is getting more and more attention.The True Random Number Generator(TRNG)provides protection for the information security of IOT devices from the source.TRNG based on jitter of ring oscillator(RO)is widely used because of its simple structure,easy implementation and good randomness.However,the existing TRNG based on the RO jitter generally has the problem of large power consumption,and IOT devices are often sensitive to power consumption,therefore,in the application of IOT,the power consumption of TRNG based on RO jitter needs to be reduced to adapt to the application requirements of IOT devices.In this thesis,aiming at the power waste caused by invalid quantization due to the oscillation period deviation in the existing TRNG circuit based on RO jitter,a low-power entropy source circuit based on temperature compensation and phase self-correction and a low-power entropy source circuit based on fine-grained regulation of oscillation period of current starved ring oscillator(CSRO)are designed.Finally,a ultra low-power true random number generator for IOT application is designed.Firstly,for the problem that the frequency and jitter of the CSRO in the entropy source circuit are greatly affected by the temperature reversal effect,this thesis designs a voltage bias circuit to improve the temperature stability of the CSRO frequency and ensure the jitter in the circuit.Then the phase self-correction circuit is designed to eliminate the accumulation of CSRO cycle deviation,thereby reducing the waste of power consumption in the quantization circuit.Then this thesis designs a low-power entropy source circuit based on fine-grained adjustment of the CSRO oscillation cycle.By fine-grained adjustment of the CSRO cycle,the cycle deviation is reduced,which further reduces the power consumption in the quantization circuit.Finally,this thesis designs a calibration circuit that can reduce the deviation with fine granularity,and gives the circuit calibration process.Based on the SMIC40 nm CMOS process,the Cadence Virtuoso software is used to perform circuit diagram design and pre-simulation,layout design and post-simulation on the ultra low power true random number generator designed in this thesis.At the same time,a digital-analog hybrid simulation platform was built to collect random numbers and perform NIST randomness detection on the collected random numbers.The experimental results show that in the range of power supply voltage 0.8V to 1.1V,the TRNG circuit designed in this thesis has a random number generation rate of more than 1Mbps at each process angle,power consumption is less than 12 u W,and single-bit power consumption is less than 1.2p J/bit.At the same time,the collected random numbers passed all the test items of the NIST SP800-22 test set.At normal temperature of 27? and TT process angle,when the power supply voltage is 0.9V,the single-bit power consumption of the TRNG circuit in this thesis reaches a minimum of 0.56 p J/bit.At this time,the random number generation rate is 3.17 Mbps,and the power consumption is 1.78 u W.