Research On Lifetime And Performance Improvement For High-density Non-volatile Memory

The rapid growth in the core count of many-core processors has enabled applications with large numbers of threads that demand a large capacity of the memory system.The scalability of the existing DRAM technology has reached the limits of the CMOS fabrication technology,beyond which more errors and reliability problems will ensue due to process variation.Several studies have shown that leakage energy grows with the memory capacity,dissipating as much heat as dynamic energy,and is a large contributor to the operational cost.To address these problems,new non-volatile memory(NVM)technologies,such as Phase-Change Memory(PCM)and Resistive Random-Access Memory(RRAM),have been proposed to alleviate the large leakage energy and poor scalability problems of the traditional DRAM technology.The emerging NVM technologies have many salient features,such as low-cost,shock-resistance,non-volatility,high density and power-efficiency,which hence are considered as viable alternatives for the design of main memory.However,the limited endurance and long write latency are the major obstacle to NVM applications.With the development of manufacturing technology,the Multi-Level Cell(MLC)technique and advanced low-process(e.g.,sub-20 nm)manufacture will be widely used in NVM devices,and the density and capacity of NVM are likely to increase exponentially.However,the high-density techniques cause that the cell endurance is severely shortened and varies widely,which further deteriorates the lifetime of NVM systems.To alleviate the poor life-time of NVM systems,wear-leveling technique is widely used.The wear leveling attempts to write the upper-level write access evenly into the underlying NVM cells,hence extending the lifetime of NVM systems.However,according to our analysis,the existing wear-leveling algorithms are not suitable to the MLC NVM and Low-Process NVM systems.To prolong the lifetime of MLC NVM systems,we propose a tiered-based Self-Adaptive Wear-Leveling algorithm(SAWL).On MLC NVM systems,the wear-leveling algorithms must substantially decrease the wear-leveling granularity to mitigate the imbalanced writes across the entire memory,which significantly increases the size of the address mapping table.As a result of the extremely large table and very small SRAM in the memory controller,the basic architecture must store the entire mapping table on the NVM devices,leading to unacceptably severe performance degradation due to the very long address translation latency.To address these problems,SAWL leverages a novel tiered architecture that stores the complete address mapping table in main memory(DRAM or NVM),and uses a small-sized SRAM to buffer the recently-used address mapping entries to prolong MLC NVM lifetime by decreasing wear-leveling granularity.To improve the hit rates of SRAM and mitigate the performance degradation,SAWL dynamically tunes the wear-leveling granularity so that the SRAM cache can accommodate more addresses.The experimental results show that SAWL improves the lifetime of MLC NVM systems to 93%of the maximum lifetime and only incurs 5%IPC performance degradation.For the Low-Process NVM systems,we propose a Weight-based Algebraic Wear-Leveling(WAWL)scheme to improve the lifetime ofNVM systems.Traditional wear-leveling schemes are not suitable for Low-Process NVM systems with endurance variation.Since they aim to uniformly distribute the number of writes to every line,the weakest cell will fail much earlier,resulting in severe lifespan degradation.To address this problem,WAWL improves the lifetime of NVM systems by balancing the wear rates(write counts/endurance)of mem-ory cells.The WAWL divides the entire memory space into many regions,and gathers the memory cells with the same endurance into a region.When the number of writes of a region reaches the swapping threshold(i.e.,the swapping interval),the algorithm randomly selects a region to be swapped,and the offsets of the memory lines within the regions are changed simultaneously.By studying the appropriate swapping intervals and chosen probabilities in experimental pattern,WAWL significantly increases the NVM lifespan and improves security with slight performance degradation and affordable hardware overhead.The experimental results show that under the malicious attacks and general applications,WAWL improves N-VM lifetime to 66%and 83%of the maximum lifetime.Given that the long write latency and the wear-leveling overhead decrease NVM perfor-mance dramatically,we propose a Write Priority overlap Read(WPoR)scheduling scheme to improve I/O performance of NVM systems.Recent studies propose a multi-partition archi-tecture within each bank to enhance internal parallelism.However,conventional scheduling schemes fail to exploit the advantage of multiple partitions and incur inefficient bank utilization.WPoR preferentially serves for a write request in one partition and allows other partitions to perform as many read requests as possible within this partition's program duration.Experimental results demonstrate that WPoR scheduling performs better than the state-of-the-art scheduling policies in terms of memory throughput and system IPC.Finally,we design a reconfigurable NVM simulator,called NVMsim,which can accurately simulate the wear-leveling algorithm,cache replacement algorithm and request scheduling strategy.In addition,NVMsim is able to measure read and write latencies,IPC performance and lifetime indicators.Compared with existing simulators,NVMsim runs faster with accurate results.The proposed algorithms of our paper are evaluated on this simulator.