Research And Implementation In Wear Leveling Systems For Non-volatile FPGA

With the increase of the application scale of Internet of things,the computing nodes of Internet of things terminal have higher requirements for computing power,energy consumption and storage resources.Therefore,hardware programmable circuits with low energy consumption,high performance and high flexibility play an important role in emerging edge computing mode of Internet of things.Benefiting from the rapid development of semiconductor process technology,the scale of FPGA's configurable resources has increased sharply,which enables FPGA to map more complex logic to handle more complex tasks.Since Static Random Access Memory(SRAM)based FPGA has limited density and comparatively high leakage power,researchers have proposed FPGA architectures based on emerging Non-Volatile Memories(NVM)to satisfy the requirements of data-intensive and low-power applications.Among all components,Block RAM(BRAM)has the severest endurance proble.Unluckily,traditional wear leveling strategies cannot be directly applied to non-volatile FPGA because it may induce large performance overhead.In this thesis,we propose performance-aware wear leveling schemes for nonvolatile FPGA to improve its lifetime.In addition,we develop a configuration file generation system to implement these schemes.Procedures including static analysis,wear leveling guided placement,reconfiguration are discussed.In order to ensure the continuity of the program,we propose a feasible scheme to support configuration switching and runtime data reserving.The experimental results show that the proposed wear schemes can achieve 46%higher lifetime improvement and simultaneously 11%lower performance overhead than the existing schemes.