| The work of this thesis is funded by some research program in advance, someadvanced research fund, and some science and technology research project. Theapplication background is the processing of complex electromagnetic signalreconnaissance, which is a complex and intensive computing characterized with largeblock size, irregularity and dependences. The research aims to design a miniaturized,low power and multi-functional broadband satellite electronic reconnaissance system.The research focuses on the key technologies of reconfigurable computing applicationsin broadband satellite electronic reconnaissance based on the commercial FPGA chips.The research includes complex signal processing and computing features analysis,reconfigurable computing models and application frameworks, the optimization ofreconfiguration overhead, and the design of guided and intelligent signal reconnaissancesystem based on dynamic reconfiguration. The research includes the following aspects:The first aspect is the complex signal processing and computing featuresanalysis, and an advanced process of broadband signal passive reconnaissance isproposed.In this part, the developing trends of electronic reconnaissance satellite payloadand requirement is analysed in-depth, and major characteristics for some typicalreceiver and signal processor are studied. And then the limitations of unidirectional anddetermined signal processing in traditional signal system are drawn out. In the followingthe relevant algorithms of real-time spectrum analysis technology in signal detectionsystem and the demands of being reconfigured are analyzed. On this basis, a novelprocessing structure of "two-stage configurable signal processing and limitedconfiguration point" is proposed, which is helpful to integrate two types of electronicreceiver structure, and a variety of operating modes into one system, and makes itpossible to realize fast switching among multi-modes through dynamic reconfiguration.The system resource utilization is effectively improved, the system size and power arereduced, also the system flexibility is improved greatly by this design.The second research is the reconfigurable architecture about broadbandelectronic reconnaissance system with above-mentioned advanced signal process.Aimed at the complex and intensive computation, the Reconfigurable Extended SoPCHybrid structure model and the Broadband Signal Reconnaissance ReconfigurableComputing Model(BSRRCM) are proposed.There is a fixed coupling relationship between CPU and RFs for the traditionalclassification of RCSA. It’s easy for loose coupling architecture to be extended, but it’sdifficult to balance between the controllability and the system performance; while it’sflexible to control in tight coupling architecture but the computability is limited. In this part, the advantages and limitations of several typical architecture of RSCA iscompared and analyzed, and then the Reconfigurable Extended SoPC Hybrid structureModel is proposed. In this structure model, the embedded processor (eCPU) of SoPCchip acts as the system configuration controller, and the FPGA chips act as extensioncomputing resources. The commercial interface IPs is used to achieve an independentconfiguration path and data path, and there are different degrees of coupling relationshipbetween eCPU and RFs. Thus, the flexibility of multiple configurations and the qualityof communication are provided at the same time.Based on above extended SoPC hybrid structure, the Broadband SignalReconnaissance Reconfigurable Computing Model (BSRRCM) is proposed, whichabsorbs advantages of the stream processing model and spatial computational model.The main function of BSRRCM is the automatic mapping from calculation to the extendSoPC hybrid structure platform driven by application. BSRRCM supports multi-leveldynamic reconfiguration strategies including parameter, partial modules and thecomplete recongfiguration of the chips. This multi-level reconfiguration allows thesystem to meet multi-functional application requirements and makes the system morescalable and flexible. BSRRCM is process-oriented rather than task-oriented computingmodel, so it can avoid a lot of overhead due to the frequent configuration tasksswitching, and has good search performance.The third part is about reconfigurable computing application framework. Toaddress the unified management of software and hardware, realize the reuse offunctions and reconfigure the system rapidly, a functional level reconfigurableapplication frameworks is built.The BSRRCS-RCAF provides four types of public service system:○1Theautomatic machine of BSRRCM, with the function of automatic capture of theapplication requirements through the design view, the automatic realization ofBSRRCM through the controlling agency, and the unified management of RFs;○2Theautomatic machine of effective integration and unified management of various types ofinterfaces;○3The multi-level dynamic reconfigurable strategy;○4The scalable libraryof components of configuration staged processes and the algorithm modules on thereconfiguration points, which are stored on the smart chip-outside configurationmemory (CF card).Based on these public services, the top-level users need not care about theunderlying implementation details on the platform of hardware.They can custom thesystem design according to the requirements of each application and achievementpartially so called “visualized design”. BSRRCS-RCAF also enables the unifiedmanagement of the system software, hardware and interfaces. The components inlibrary can be expanded and updated, but the platform structure will not be fundamentally changed, which greatly achieves the re-use in the field of computingresources and capabilities within the specific scope of application, and significantlyimproves the system flexibility and scalability.The forth part focuses on the optimization of reconfigurable overhead.The time overhead for multi-level dynamic reconfiguration are analyzed and testedin detail. Based on the multi-region design on the commercial single-context FPGA, thePlatform-Based Multi-Context(PBMC) technology is proposed, which could hide partof reconfiguration overhead, or to improve the effective utilization of resources.Taking into account the the larger blocks size and the fact that there are manycomputing tasks with higher serial degree in the signal reconnaissance applications, thecomparison of the total time and the effectively resource utilization of completing avariety of typical tasks is analysed indepth. Then a set of guides about the design ofBSRRCS_RCAF are concluded and verified by simulations.In this part of the final, PBMC technology has been used to solve two kinds ofproblems in the broadband signal reconnaissance system. One is to solve the calculatingresources insufficientness with the large-size blocks, and the other is to reduce the timeoverhead when a lot of algorithm modules with similiar functions are repeatedlyscheduled in the system. In both cases, the desired results are achieved.In the fifth part, a prototype of the reconfigurable guided signal reconnaissancesystem design is proposed and realized.In the final part of this thesis, based on the dynamic reconfiguration and the multi-dimension electronic intelligence from real-time spectrum analysis, a prototype of agradually guided complex signal sorting and recognition system is designed. Theprototype verifies the idea of reconfigurable guided signal reconnaissance systemdesign.The research of thesis shows that the reconfigurable computing technology can besuccessfully applied to the electronic reconnaissance satellite payload informationprocessing platform, and other varieties of small, multi-functional signal processingsystem. It is a key technology for further development for electronic reconnaissanceprocessing and has important theoretical and practical significance to improve thecapabilities of satellite payload. The research approach and results can be extended tothe airborne, ship-based, vehicle and other miniaturized systems. In a word, it has thevery large application prospects. |
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