Research On Static Power-and Contention-Aware Real-Time Scheduling In NoC-based Multicore Systems

Due to high levels of integration and complexity, the design of multi-core SoCs has become increasingly challenging. In particular, energy consumption and distributing a sigle global clock signal throughout a chip hava become major design bottlenecks. Using on-chip interconnection networks in place of ad-hoc gloal wiring structures the top level wires on a chip and facilitates modular design. With this apporach, system modules communicate by sending packets to one another over the network. The structured network wiring enable the use of high-performance circuits to reduce the energy consumption.Currently, the communication contection and network latency are often overlooked to achieve better energy consumption performance in the research of energy-efficient of NoC-based multicore architecture. But in the actual systems, regulating voltage/frequency by DVFS may result in missed deadline of the scheduling. The additional schedule length may generate more energy.This paper presents a power-and contention-aware real-time scheduling algorithm in the context of NoC-based multicore architectures. The proposed algorithm tackles the issue of communication contention on the network and aims at effectively reducing the system-level energy consumption while satisfying timeliness requirements. It not only maps the tasks onto processor cores, but also determines the routing paths and priorities of the communication data between tasks with precedence relationships. Next, the initial processor core and link speed can be calculated while meeting deadline constraints. Then adjust the start and finish time of tasks and communications.Experimental results show that our proposed algorithm effectively improves the scheduling performance with respect to system-level energy consumption and deadline requirements can be satisfied simultaneously.