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Research On The Charge Trap Non-volatile Memories Design And Ionizingradiation Degradation Characteristics

Posted on:2014-04-21Degree:DoctorType:Dissertation
Country:ChinaCandidate:F Y QiaoFull Text:PDF
GTID:1228330452969332Subject:Electronic Science and Technology
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Exposure to total ionizing dose (TID) and single event effect (SEE) radiation willcause charge loss from flash memory cells and functional failure of the memory chip.SONOS cells, based on discrete charge storage mechanism, are more radiation tolerantcompared to floating gate cells, thus is considered as a promising candidate for spaceapplications. In this thesis, we systematically investigate the radiation characteristics,degradation mechanism and radiation hardening technology of SONOS cells andmemory circuits, and finally design a radiation-hardened chip which satisfies all theradiation resistance requirements for space applications.In this thesis, we did research on the radiation characteristics, degradationmechanism and radiation hardening method for home-designed0.13μm SONOSmemory cells and a4Mb memory circuit. Research results on the memory cells indicatethat the total ionizing dose radiation degradation of SONOS cells includesthresholdvoltage (VTH) shifts loss due to charge loss and leakage current increase due to parasitictransistor effect at the edge of the isolation oxide. Combined with the radiationcharacteristics of the read path in the flash circuit system, we found that the main dataerror mechanism is the “0” state read failure caused by VTHloss from the programmedstate in our array. Combined with the HV generation circuits and HV paths radiationcharacteristics, we found that the write failure is due to the increased TID inducedleakage of the HV pass transistors in the column direction, which leads to currentoverloading of the charge pumps and therefore collapse of the program/erase voltage.SEE radiationexperimentshave shownthat SONOS memory chips have a better singleevent upset (SEU) tolerance, but partial latch up will cause an increase of the chip activecurrent, leading tofunctional failure. Based on these results, we proposed specificradiation hardeningmethods for the device process, circuit and layout levels andsuccessfullydeveloped a radiation hardened chip. Experimental results show that thetotal ionizing radiation tolerance of this chip is higher than100krad (Si) while the SEEtolerance is higher than42MeV·cm2/mg.For hardening the process, we proposed a new PD-SOI based DTI-LOCOScombined cross-isolation method, which eliminates the TID radiation induced isolation leakage and leads to a reduced area overhead. Therefore, itis suitable for makinghigh-density radiation hardened memoriesby combining the integration of SOI andSONOS process technology. Based on the proposed method, a256Kb EEPROM testchip was designed and fabricated, and the experimental results have confirmed thevalidity of this approach.For achieving higher densities, we have studied novel3D-SONOS cells withvertical channel.On these devices, we did researchon program/erase (P/E)characteristics, reliability issues and finally the TID radiation response. Furthermore, wehave investigated the reliability degradation mechanisms and the tunnel oxide qualityprocess. Experimental results show that3D-SONOS with GAA (Gate-All-Around)structure has larger VTHmemory window compared to conventional SONOS cells, andthey are immune to radiation induced leakage current. Therefore, they aresuitable forhigh radiation dose applications.
Keywords/Search Tags:Charge-Trapping-Memory (CTM), Si-Oxide-Nitride-Oxide-Si(SONOS), 3D-Flash Cell, Total-Ionizing-Dose (TID) Radiation, Single Event Effect(SEE)
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