Study Of Multilevel Cell Storage Technique And Device Physics For4-bit SONOS Memory

In recent years, charge trapping memories with low-voltage, low-cost and high reliability advantages have been extensively investigated, and in the future they may become an alternative to replace the traditional floating gate flash memory. Nitride read only memory (NROM) as a unique localized charge trapping memory, applies multi-bits cell and multilevel cell programming techniques simultaneously. It achieves4bits storage per cell, greatly enhancing the storage density. However, as the cell channel length is scaled down to90nm, NROM is confronted with a lot of problems. Shallow trench isolation (STI) process seriously impacts the performances of NROM edge cells; second bit effect seriously affects the multi-bits cell storage characteristics; endurance and retention characteristics are further degenerated; the main charge loss mechanisms are still not very clear, and so on. To solve these issues, a series of researches have been carried out in our work. The obtained main results are as follows:(1) It is experimentally found that the edge cells adjacent to STI corner have significantly lower channel hot electron injection programming efficiency than central cell far from STI. It is also found that initial threshold voltage (Vth) distribution of edge cells is apparently inconsistent compared with central cells. With the aid of TCAD process simulation, it is believed that boron segregation which reduces the boron doping of edge cell active area is the main cause of lower programming efficiency of edge cells. It is also believed that the higher STI compressive stress leads to the decrease of electron mobility of edge cells active area. The boron segregation and compressive stress induced by STI are thought to be responsible for threshold voltage distribution discrepancy between the edge and central cells. In order to reduce the STI-induced impact on the edge cells, an additional boron implantation in STI region is proposed as an effective solution. By adjusting the dose and energy of the additional boron implantation, the boron loss in the edge cell active area is compensated. As a result, the programming efficiency of edge cells has been remarkably improved. Additionally, two influences of boron segregation and compressive stress on initial Vth distribution cancel out each other. Hence, the Vth distribution discrepancy between edge and central cells has been substantially minimized.(2) It is experimentally found that the injected electrons profile in conventional channel hot electron programming is relatively wider than the injected holes profile in band-to-band tunneling hot hole injection (BBHHI) erasing due to the secondary electron injection (SEI) effect. Thus, after repeatedly program/erase (P/E) cycling, residual charge buildup occurs, which aggregate the second bit effect and leads to the serious degradation of cycling endurance and retention. In order to suppress the SEI effect and obtain the good matching of injected electrons and holes, an improved CHEI programming with the positive substrate bias is presented. Compared to the conventional CHEI programming, the substrate of NROM device is applied to1.5V instead of0V, which availably restrains the SEI effect. At the same time, the source is tied to1V to keep the source/substrate junction from forward-biasing, which greatly reduces programming power. The experimental results show that the proposed programming method significantly improves the cycling endurance and retention. In addition, the second bit effect is also inhibited. It is important to note that the improved CHEI programming method is completely compatible with the incremental-step pulse programming (ISPP) technique, so it is well suitable for multi-level multi-bits cell programming in the actual4-bit/cell NROM products. (3) A novel high density eight-level cell programming method is proposed. This new method first uses a double-side BBHHI mechanism for a uniform erasing. The generated holes from band-to band tunneling uniformly inject into storage layer above the channel and NROM device is erased to the state with Vth of-0.5V. Then, with the state of negative Vth as new initial state, the localized multi-level programming and erasing operations are performed to achieve the eight-level cell storage, so3-bit storage in a single cell is obtained. The measured results demonstrate that this new operating mode provides a double memory window over the conventional four-level cell programming. The eight-level cell still has a large sense window after1000P/E cycles, with good cycling endurance and data retention characteristics.(4) The charge loss mechanisms of NROM device have been investigated and the data loss retention model based on charge lateral redistribution has been confirmed. Experiments found that when the good match between injected electrons and holes distribution is achieved, the injected electrons can be effectively erased and1-pole charges distribution is obtained, which greatly improves the data retention. If the profile of injected electrons is wider than injected holes, the injected electrons cannot be erased completely. As a consequence that residual electrons and holes accumulate and a3-pole electron-hole-electron distribution is formed. Since the energy of holes trap is0.3eV lower than that of electrons trap, the accumulated holes are easily excited to the conduction band. Subsequently, holes laterally transport in the nitride layer and recombine with injected electrons, which results in the serious degradation of data retention. Experiments also present that when the profiles of the injected electrons and holes are matched and the traps of oxide and interface states is increased, there is not obvious degradation of data retention. It can be further confirmed that the lateral redistribution of charge in the nitride layer is the main cause of charge loss, rather than the vertical loss through interface states or oxide trap-assisted tunneling.