Research On Key Technology In Network On Chip Monitoring System

As CMOS technologies move toward deep sub-micron and nanometer regime, reliability has become one of the most crucial issues in very large scale integration (VLSI) systems. With the fast development of integrated circuits, the feature sizes of transistor and wire shrink rapidly, the power supply voltages reduce continuously, and the operational frequencies increase dramatically. VLSI circuits become more and more vulnerable to a variety of faults. Network-on-Chip (NoC) achieves highly integration of various multi-processors and functional modules. Also, on-chip communication becomes more and more vulnerable to a variety of sources of interferences, and even leads to system malfunction. Consequently, it is necessary to develop some mechanisms accordingly to enhance the reliability for Network-on-Chip system. Monitoring system of NoC extracts information regarding the operation of a network for many different applications, such as verification and debugging, fault-tolerant scheme, run-time reconfiguration and parameters adaptation.Based on the study of NoC and available monitoring technology, the key circuits of monitoring system for NoC have been analyzed and designed. The main contributions are as follows:1. Based on the study of available network monitoring system, the functions and structure of a NoC monitoring system are discussed in this paper. The monitoring system can provide two types of services by monitoring the on-chip data transmission and network status. One is to provide diagnostic and location service by accumulating the fault events of on-chip communication. The other one is to provide dynamic routing computation based on the fault information and traffic status. The light weight property, coverage, robustness, and independence of the proposed monitoring system are also discussed in this paper. A multi-level hierarchical monitoring system for NoC is proposed in this paper. The functional levels are link, router, group and chip levels.2. The fault types and sources are analyzed in this paper. The available fault detection and processing schemes are also discussed, including fault detection/correction and retransmission, fault location and dynamic routing. To overcome the drawback of available schemes which can not distinguish between transient and non-transient faults, a novel NoC link level monitoring circuit based on fault thresholds is proposed. A router level monitoring circuit is also designed to locate the fault in the chip. The light-weight property, coverage, robustness, and independence of the proposed design are elaborated.3. The network monitoring system needs to detain and avoid the fault resources, such as router or link in a NoC, by dynamic routing computation. The available study of dynamic programming (DP) circuit for NoC routing is analyzed. A current-mode dynamic programming circuit is designed to provide a powerful, low-cost and high-speed solution. As a basic computational unit of current-mode dynamic programming (DP) circuit, a novel CMOS current-mode continuous time Winner-take-all/Loser-take-all (WTA/LTA) circuit is presented. A regenerative circuit is used to amplify the difference of input current and accelerate the comparison, which makes the WTA/LTA with a high resolution and high speed. The output current of WTA/LTA circuit is selected to reduce the propagation error caused by mismatch, which improves the precision. The inherent high-resolution, high-speed and low-power capabilities of the proposed design are ideal for a variety of multi-input applications. Using proposed WTA/LTA circuit as a basic computation unit, the performance of dynamic programming network can be improved greatly.4. Existing current-mode WTA/LTA circuits usually use multiple current mirrors and employ binary-tree structure to expand the design. The mismatch becomes a serious concern to affect the precision and resolution of a WTA/LTA circuit. To overcome these problems, three novel current-mode WTA/LTA circuits without using current mirror are proposed in this paper. The first one employs the positive feedback of regenerative circuit to compare the input current, and select the output based on the comparison result. A binary-tree structure is also used to expand the design. The second one also employs the positive feedback of regenerative circuit to compare the input current. But the output current is acquired by using rectifier circuit. A new concurrent multi-input structure is also proposed. The third one converts input currents into time domain signals based on integration method. Arbitration circuit is used to distinguish the earliest signal corresponding to the largest input current. The output is also selected based on the comparison result. This circuit can be expanded by using binary tree structure. To further reduce delay, a concurrent multiple input WTA structure is also designed. These three circuits overcome the drawback of existing WTA/LTA circuits which employ multiple current mirrors, to provide better precision and resolution, and lower latency. It is ideal for a variety of embedded intelligent applications.