Low temperature measurement of silicon/silicon dioxide interface roughness and interface trapped charge in metal-oxide-semiconductor devices

This thesis discusses the use of low-temperature electrical measurements on silicon metal-oxide-semiconductor field-effect transistors (MOSFETs) to determine properties of the Si/SiOA novel, non-destructive method was used to probe the interface roughness of intentionally roughened MOSFETs. This method uses low-temperature (1 Kelvin) measurements of source to drain resistance in parallel and perpendicular magnetic fields to determine the weak localization correction to the channel conductivity. This correction can be related to the spatial fluctuations felt by the channel electrons. Devices with an RMS roughness up to 8 angstroms have been made by using an argon RF sputtering step before gate oxidation. To verify the effectiveness of this technique, the roughness measured with weak localization has been compared to roughness values from AFM. Both techniques give comparable results. Transistor characteristics, such as 4.2 K mobility, have also been measured and compared for devices for which the interface roughness is known. The relevant characteristic length scales for these measurements are discussed.In addition, low-temperature gate to channel AC conductance measurements have been used to detect interface traps formed after x-ray irradiation. Most trap detection methods performed at room temperature measure traps with energies within 300 to 400 meV of the midgap. Performing capacitance-voltage and conductance-voltage (CV-GV) measurements on MOS transistors at 4.2 Kelvin can extend this range to reveal information about trap levels in the silicon conduction band. Conductance measurements on MOSFETs show a feature which appears after x-ray irradiation, indicating the presence of conduction-band interface traps. An equivalent circuit model has been solved analytically and used to obtain the trap density and time constant.