Resource Allocation For Chip Multithreading Architecture

With the ever-increasing transistor density and ever-developing processor architecture, the research and design of processor is coming into a CMT (Chip Multithreading) era. CMT empowers multiple threads to run simultaneously within one chip, sharing and competing for various resources on chip, herein improving resource utilization and the overall performance significantly. Nevertheless, some new hazards are introduced with the design and implementation of parallel thread running. First, various on-chip shared resources undergo higher pressures in such aspects as size, complexity, power, latency, etc. Second, inappropriate resource competition usually leads to resource misuse, thus having a strong impact on resource efficiency, fairness, and overall performance. To overcome these hurdles, this thesis focuses on resource allocation for CMT architectures, and it aims at alleviating the design and access pressures on the shared resources, improving resource efficiency and fairness, reducing implementation cost, boosting overall performance, and enhancing allocation safety.First of all, a cycle-by-cycle simulator called OpenSimCMT is designed and realized for the simulation of CMT architectures, which severs as a fundamental platform for CMT research. And basing on the platform, the following research and designs are carried out.Thread-level parallelism further increases the design and access pressure on the register file. It is fairly hard for the traditional register renaming techniques to meet the ever-increasing register demand from CMT architectures, and the register file is becoming a potential bottleneck for future higher performance processors. Taking advantage of the distribution of register values, the feature of register allocation, and the complementary from multiple threads, this thesis proposes a scheme called Multi-usable Rename Register with 2-Level renaming and allocating (2L-MuRR), which nearly doubles the capacity for each register, alleviating the design pressure on the register file in CMT significantly.Resource misuse depresses both resource efficiency and overall performance for CMT processors. This thesis gives an in-depth analysis on the resource...