Research On Some Key Techniques In Mesh NoC Platform

Network-on-Chip is a new on-chip communication architecture for the multi-core SoC,it brings a new solution to the problem which the traditional shared bus has in delay,communicaiton performance bottleneck and design efficiency for the ultra-large scale circuit design. This thesis firstly depicts the research art of NoC, the shift of SoC design methodology and the design flow of NoC centric system-on-chip. Aiming to the 2D mesh NoC topology, we analysis it's performance character, routing algorithm, and the router's power and NoC's performance model, also we compare them with the shared bus architecture for the performance and cost.Low power design is a trend for the ultra-large scale integrated circuit design, specially for the embedded system, mobile and hand device. For the NoC based system design, we can reduce the NoC energy consumption at the different design layer, which includes physical layer, link layer, network layer and application layer. In this thesis, we exploit the low power design technology in the NoC's application layer and network layer. The main works of this thesis are follows:First of all, data integrality become a serious problem under the ultra-deep micro semiconductor technology. For the new NoC communication architecture, we propose an adaptive link data protection method. It can be adaptively trade-off between the energy consumption and reliability according with the communication condition of data links, which make NoC satisfy the requirement of reliability and minimize the energy consumption. This also reduces the energy consumption of NoC based SoC.Secondly, we propose a delay computing method of NoC packet based on the characteristic of the NoC's network communication. Through analyzing the reach curve of input packet and the serve curve of NoC's router, the method computes the packet transporting delay through utilizing the network calculus theory. Furthermore, we exploit the delay computing method for various arbitration strategy in the NoC router, and compare the delays with the cycle accurate simulation results. It shows the accuracy of delay computing based on network calculus.Moreover, we propose a two step PSO based low power and link-load balance algorithm for IP core mapping and routing path allocation. IP core's mapping and routing path's allocation are the two key steps in the NoC based system design. For the 2D mesh NoC, we propose the mathematical description for the NoC's communication energy consumption and link-load balance. Meanwhile, we also solve the PSO particle denotation for the IP core's mapping and routing path allocation. But for the various application, the communication flows among all IP cores have the great difference, thus for the purpose of the most optimized performance, we must configure the algorithm parameter according with the specific application.Finally, for the irregular 2D mesh NoC, we propose a low power deadlock-free routing algorithm EA_TP. EA_TP is based on the turn-prohibited deadlock free routing . According with the link length and communication volume, and it prohibits the appropriate turn and guarantee the NoC's full connection. Then, EA_TP adopts the Dijkstra shortest path algorithm to customize all the flows routing path. EA_TP constructs the routing path with routing table, it prevents the irregular NoC deadlock and keep a low area cost while minimizing the communication link energy consumption.