Network Calculus Applied Research For Network On Chip

At present, with the chip internal audit and Cache capacity increases, on-chip interconnect pressure increasing, the traditional interconnect become unsuited to the current needs. The bus and cross switch are typical conventional interconnection. The bus can only handle a message sending from a node during each clock cycle. For processors that have more than 8 cores, the throughput of bus connection is too low. The area overhead of crossbar switch is proportional to the number of port, so for the 16-core processor, the area overhead of crossbar is too large. Network on chip become an important mean to solve the chip interconnect problem.Network on Chip(Noc) design mainly include topology design, routing design and flow control. Mesh and Torus structure is the most frequently used Noc topology, because its layout is simple, also it has high link utilization and scalability. Routing routing algorithm is an important part of the design, which determines the packet transmission path,also the routing algorithm decide many features of NOC such as connectivity and selfadaptive. How to measure the delay and backlog characteristics of the routing algorithm and reasonable assessment of the routing algorithm is important for network on-chip design. Meanwhile, different topologies are also greatly affected the performance of on-chip networks, how the delay parameters of the topology were measured is also important to its design.In previous studies, the on-chip network parameters are measured mainly by the simulator which may have high usage rate of time and resource, also its analysis is about the average network performance parameters. In Qos services of the network, the worst-case performance parameters have a higher reference value than average parameter. Network calculus is a network performance analysis tool based on the minimum plus algebra and maximum plus algebra, and it has a profound theoretical background. Compared to traditional simulator methods, the use of network calculus to analyze the network takes less time and resources, and can greatly promote the Qos research.In this paper, we analyze the common on-chip network routing algorithm using deterministic network calculus as a tool, and put forward a common routing algorithm evaluation algorithm, compare and analyze it with results generated by Omnet + + tool. Considering the complexity of the 3D Noc structure, we analyzes the delay parameter, and do a performance comparison for 3D MMT 3D RNT with other properties of the two different structures integrated. The main research results include the following aspects:1. Used Deterministic network calculus method to analyze a wide range of on-chip networks 2D Mesh structure for the two kinds of routing algorithms, XY and XY- YX routing algorithms, comparative analysis the network traffic end to end delay and node backlog of the two routing algorithms,.2. Proposed a generic algorithm to evaluate on-chip routing algorithms, and compared the results of the algorithm and results obtained by Omnet + + simulation, the algo- rithm compared to the traditional method of simulator has low time complexity, less resource to get the worst-case performance of the network, has a great significance to Qos service of the network.3. Analyzed delay of two complex 3D chip network structure, combined with other relevant parameters to get a comprehensive comparison of the two structures.This article is for on-chip network communication needs, the use of network calculus approach to on-chip network routing algorithms and 3D structures were studied, delay,backlog in routing algorithm and delay of the 3D structure were studied, and do simulation experiments. The research results for the evaluation of on-chip network routing algorithm and the on-chip network structure is of great significance, and has certain application value for applied research of the network calculus.