| In the past few decades, the semiconductor industry kept shrinking the feature size of CMOS transistors with great efforts in order to pack more functional devices onto a smaller footprint, which follows the famous Moore's law. However, it becomes extremely difficult to ensure the correct functionalities of fabricated circuits in today's integrated circuit (IC) technology, because the increasing variations from the manufacturing have introduced inevitable and significant uncertainties in circuit performance. Moreover, the requirements of lower power consumption and higher operating frequency for today's mobile devices demand tighter performance constraints on fabricated circuits. Therefore, reliable and efficient statistical analysis methodologies are highly sought to enable IC designers to predict the stochastic behavior in fabricated circuits under random process variations before entering expensive manufacturing.;In this research, the impacts of process variations are studied in the contexts of failure analysis of memory circuits, stochastic behavioral modeling and variational capacitance extraction and novel solutions to these contexts are presented. In particular, memory circuits require an extremely small failure probability for one single cell due to their high replication count on a small footprint, thereby making it a great challenging task to provide accurate estimations. To this end, an improved importance sampling algorithm is proposed to significantly expedite the convergence rate of failure probability estimation for memory circuits without compromising accuracy. For high dimensional problems, the conventional importance sampling schemes tend to lose accuracy and become very unreliable. To fix this issue, a novel and fast statistical analysis is presented to estimate the extremely small failure probability of memory circuits in high dimensions. In addition, an efficient statistical analysis is proposed to explore the stochastic behavior of circuit designs due to random process variations. This methodology enables IC designers to accurately predict the "arbitrary" probabilistic distribution of circuit performance considering the uncertainties from the manufacturing. Lastly, parasitic capacitance has more impact on circuit performance in today's sub-micron CMOS technology, which leads to unpredictable delay variations and severe timing errors. To address this issue, a novel and fast capacitance extraction algorithm is proposed to model the geometric variations of interconnect circuits and accurately calculate the variational parasitic capacitance. These stochastic modeling and analysis methodologies can be used to analyze custom circuits under process variations in the present nano-technology era and future generations of IC technology. |
