The Design And Implementation Of High Performance Secondary Cache On YHFT-DX DSP

Nowadays, the Digital Signal Processor (DSP) has been widely used, but DSP's performance is also limited by the"memory wall"problem. To resolve this problem, multiple level memory structure is commonly used. Today, the"cache+RAM"two level memory structure is mostly used in DSP design. In DSP, the secondary memory is not only a memory, but also is in charge of the data transformation from DSP core to external memory. For this reason, how to design a high performance"cache+RAM"two level memory structure, especially a high performance secondary cache scheme, is an important problem in DSP design.YHFT-DX DSP is a high performance DSP which is developed independently by my university. It adopts Very Long Instruction Word (VLIW) architecture, whose instruction fetching packet contains 8 instructions, and it can execute 8 instructions in parallel in one cycle at most. Meanwhile, YHFT-DX DSP uses two level memory structure on chip, and the secondary memory is a 1MB"cache+RAM"memory, which is shared and can be configured. When customer is designing a program, he can adjust the proportion of cache and RAM according to the program feature. This paper presents the design and implementation of high performance cache in YHFT-DX DSP, and it contains following works.First of all, this paper reviews the cache techniques and the requisite performance in the popular DSP, and then designs and implements the miss pipeline of L2 cache on YHFT-DX DSP, which can deal requests from L1 on pipeline way, and the miss pipeline can overlap the hit cost of L2 cache effectively. The speedup can be 1.31 at most, when it deals the miss requests which access the L2 memory.Secondly, it analyses the feature of memory-access in programs, and summarizes two kinds of missing access address sequence which can be predicted. And then, it designs a stride adaptive prefetch scheme on secondary cache according to the two kinds of missing access address sequence. In DSP, the secondary cache can not see the address of memory-access instructions, so the prefetch scheme uses the line address to lookup the prefetch table, which can make the implementation of the prefetch scheme on L2 cache simply. Meanwhile, the prefetch scheme uses a confidence system to control the producing of prefetch signal, which reduces the missing rate of cache effectively. Through testing by SPEC2006, the scheme can reduce miss rate on L2 cache by 4.5%, and the speedup can be 1.3 at most.At last, it implements a stride adaptive prefetch scheme combined with L2 cache miss pipeline in YHFT-DX DSP, which contains both the miss pipeline and the prefetch scheme introduced before. The structure has the advantage both of the miss pipeline and the prefetch scheme, so it can greatly improve the memory-access performance of YHFT-DX DSP.