Study On Patterned SOI RF Power Devices

The continuing growth of mobile communications markets is motivating a steady evolution of radio frequency integrated circuits (RFIC's), and the explosion of interest in high integrated-density, high speed and low power-consumed RFIC is driving the research of novel substrate platforms for the replacement of conventional GaAs or bulk silicon technology, which will reach their physical limits. On the other hand, SOI (Silicon-on-Insulator) is becoming mainstream technology in sub-micron semiconductor technology due to its completely dielectric isolation and ideal sub-threshold slope, as well as low power-consumption. However, SOI technology has to face the problems of floating body effects and self-heating effects.Patterned SOI technology is the simplest way to overcome floating body effects and self-heating effects. In this thesis, the application of patterned SOI (PSOI) technology to RF power device was investigated systematically.PSOI LDMOS structure with a silicon window underneath p body was proposed, and TSUPREM4 and MEDICI simulation were presented. The proposed structure showed excellent electrical performance including ideal output characteristics immunity of kink effect and self-heating effect, the small signal gain reaching to 1 ldB at 2GHz, and the cut off frequency and the maximal oscillating frequency up to 10GHz and 40GHz respectively.Masks and flowing process were designed with the help of simulation results. Minimal changes were introduced to the process in order to demonstrate potential compatibility with conventional lum SOI CMOS technology. There were two principal modifications, one was to prepare patterned SOI substrate, the other was to define n- drift region.The proposed structures were fabricated on PSOI substrates prepared by selective masked SIMOX technology. Body contact SOI LDMOSFETs and bulk counterparts were also integrated in the same die to show the flexibility of PSOI technology. PSOI LDMOSFET exhibited good DC electrical performance. The output curves were flat, showing no kink effects and self-heating effects. The on-state breakdown voltage of 8V and the off-state breakdown voltage of 13V were achieved. The leakage current was about one order lower than that of bulk counterpart. RF characterization was performed using coplanar wave-guide probes, and the calibration to the probe pads was obtained through two-step de-embedding technology. The small signal gain could reach to 6dB at 1GHz, and cut off frequency up to 8GHz. The small signal equivalent circuit model was established for the further investigation on power amplifier applications.In addition, the body contact technology usually adopted by power devices was improved, where body contact regions were formed by p body implantation, that is, source region was selectively implanted by n+ in order to conserve some p type regions. SOI LDMOSFETs fabricated with this body contact technology showed no kink effects when gate finger length was 10um or 20um, but kink effects appeared at the gate finger length of 50u.m.At last, high k dielectric films on SOI substrates for the replacement of conventional gate dielectric of SiO2 was studied. Post deposition anneal (PDA) can effectively reduce traps density, make surface smooth, but lead to the growth of SiO2 at the interface. Hf silicate or Hf silicide were not found at the interface.