Wideband Digital Receiver Dual Signal Data Rate Conversion Technology And Research,

With the development of Electronic War (EW) technology, more and more attention is concentrated on the research and development of wideband digital receiving technology (WDRT), which is very important for the detecting and intercepting of Radar signals in the battle field. As one crucial part of WDRT, the research and realization of data rate conversion technology (DRCT) is presented. This dissertation studies two kinds of DRCT by applying the following two approaches: bandpass sampling (BS), wideband efficient digital downconversion (WBEDDC).The main works of the dissertation include: 1. Based on the environment of battle field, the necessity to process two simultaneous input signals, which is the demand of detecting and intercepting Radar signals, is discussed. 2. Two approaches to realize Multi-signals BS, based on the theory of intermediate frequency of sampled signals and spectra arrangement of sampled signals, are studied. DRCT base on BS is studied. It is proposed that A/D with varying sampling clock is required.because the bandpass sample rate shifts with the carrier frequency and bandwidth of the target signal, This brings great trouble in hardware implementation. 3. Improved DFT filer banks, designed for processing varying signals, are presented. Using DFT filter banks,filtering and down conversion are completed in the same time after decimation. And parameter varying signals can also be processed by changing the coefficient of the DFT filter banks. 4. The WBEDDC FPGA realization of dual-signals is presented. Using parallel processing downconversion structures, dual-signals can be processed easily, while band varying signals are processed with different filters based on the band. The introduction of Synplify Pro speeds up the development of the project. 5. The examination hardware system is developed, which includes system design, A/D sampling subsystem, frequency detection and downconversion subsystem, PCI data transmission subsystem. Sampling rate is doubled by two parallel working AD9430 chips. Frequency detection and downconversion subsystem realize 4.8Gbps high speed data transmission with 4 FPGA and LVDS bus. PCI data transmission subsystem buffers the data and transmit them into PC.