Research On Boolean Process And Its Application In Design Automation For Complex And High-speed Chips

The design of complex and high-speed chips requires novel theories and approaches in design automation. Boolean Process theory is recently proposed to meet this requirement. Based on Boolean Process, some theoretical extensions are made and novel techniques in design automation such as timing, test generation and basic research on verification and synthesis are proposed in this paper.Some theoretical extensions are first made in this paper, with the following concepts, theorems and models presented-Partial derivative and high-order partial derivative of waveform polynomial for describing the relation between input transitions and output transitions and redefining circuit sensitization; The concept of waveform polynomial vector for describing a circuit with multiple inputs and outputs, especially for the unified description of circuit modules; A sensitization theorem for sequential circuits for the purpose of exact timing; Theorems for transition numbers in circuits used to solve problems on noise, power consumption and etc; waveform polynomial description for sequential circuits used to give a unified form for the function and timing behavior of a sequtial circuit; And a data structure of generalized list for the representation and manipulation of waveform polynomial.Then studis on new models and new approaches based on Boolean Process in delay automation are made. Analytical delay model is improved with the new concept of sensitization, based on which delay matrix is proposed to describe the delay of circuit modules. Then introducing hierarchical delay analysis methods into delay matrix analysis, a novel exact hierarchical delay ananlysis method is presented. This approach can greatly reduce the computation time on complex problems with good exactness, especially suitable for IP based design.Conditional sensitization of paths is presented from the sensitization theorem of sequential circuits and a novel exact clocking method based on single-period sensitization is proposed. Compared with tranditional methods, it is not too optimistic or pessimistic, fit for the exact timing of high-speed circuit design. Anda retiming scheme based on the above method is also presented to optimize the timing behavior of sequential circuits. Also from waveform polynomials of sequential circuits, a precise clocking method based on multiple-period sensitization is presented.A novel noise estimation method based on Boolean Process is first presented in this paper, using transition numbers to describe noise effects. Then combined with the selection method of long sensitization paths based on waveform sensitization, a test generation approach that could generate the noisiest sensitization waveforms for long sensitizatizable paths is presented. Experimental results in this paper show our approaches can be efficiently used in delay testing for complex circuits with noise effects.In chip synthesis and verification, component maching and verificaion are basic links. It is a crucial issue to establish a unified canonical description form for different design levels with low complexity. A new method that transforms bit-level waveform polynomial to word-level polynomial model is given, allowing for simple composition. This method offers an efficient way to determine whether two descriptions from different design levels are equivalent, so component reuse, synthesis and verification across design levels can be realized.In addition, an experimental system using C language is established, including modules such as representation of waveform polynomial, decision of path senstization, delay computing, clocking based on single-period sensitization, clocking based on multi-period sensitization, test generation considering noise and transformation from bit-level waveform polynomial to word-level polynomial model. They respectively used to test models and techniques proposed in this paper.