Research On NoC Modeling And Performance Optimization

Embedded systems benefit from fast development of semiconductor technology and VLSI design methodologies, and they improve greatly and steadily in performance to meet the needs of complex and computationally intensive applications. However, the fact that the device feature size is continuously shrinking and the bandwidth requirements are increasing, challenges the traditional bus-based communication architectures. Networks on Chip (NoCs) have emerged as a promising alternative because of their excellent scalability, flexibility and transaction-level parallelism.NoCs have diverse topologies, complicated communication protocols and various configuration parameters. How to choose an optimal architecture from the enormous design space is a common and important problem in the early design stages. We present a general analytical model for large space explorations and design optimizations. It is developed based on M/M/1/K queuing system and not limited to certain topologies. It can provide useful performance information, including average latency, throughput and waiting time distribution in routers. Besides, we propose the routing path decomposition approach to analyze and quantify the influence of link dependencies on latency. It resolves the inherent dependency of successive links occupied by one packet in wormhole routing, and improves evaluation accuracy.Analytical tools model network behaviors based on statistical methods and mathematical theories. They feature high-level modeling and fast evaluation speed, and are helpful in analyzing static and quantitative parameters of well-defined systems. On the other hand, accurate simulation tools outperform in measuring dynamic and qualitative factors of complex systems. We present a cycle-accurate NoC simulator, which emulates the pipeline stages and control logic in routers at a flit level. It provides good supports for various communication techniques, such as virtual channel flow control, wormhole routing, credit-based flow control, etc. The simulator is flexible in configurations and can evaluate assorted topologies, traffic patterns and router architectures. Effects of these parameters on communication performce can be revealed intuitively through simulating NoCs with different configurations. As so. the simulator is a useful tool for designers in optimizing interconnect architectures and improving communition quality.Equipped with the analytical model and the accurate simulator, we design a throughput optimization approach based on non-uniform link capacity allocation. We first analyze the key factors which influence NoC throughput, and propose two methods of channel bandwidth planning, one is based on traffic volume, and the other is based on channel utilization derived by the analytical model. Allocation based on traffic volume only considers workload distribution, while the solution based on channel utilization takes resource utilization and link dependency into account as well as the workload. Therefore, the latter performs better in locating congestion. We present a multi-port router to connect links of different bandwidth. It employs limited-connected crossbar to reduce hardware cost. Improvement on throughput of our proposed heterogeneous NoC is validated by simulation results.