Built-in Self Test Technology Of Electronic Systems

In recent years, with the development of DSP, FPGA and other VLSI, they have been applied on national economics and national defense equipments extensively, which greatly increases the performance of electronic systems. However, at the same time they also brought a new question of testing and fault diagnosis. Traditional electronic system testing technology is plagued with many problems. The procedures are too complex, the test time is too long, the cost of testing is too high, and fault detection rate is too low. So it can not adapt to these devices as the core of electronic system test. The new theories and methods of test must be studied.Based on the study of testable design and testable design theory, this paper has been proposed electronic system BIST (Built-in Self Test, BIST) solutions. The program generates and loads test vectors, extracts the fault features to complete the test by its own electronic system resources. Research work of the automatic test pattern generation method, fault feature extraction, test sequence optimization and other aspects were carried out in this paper to solve the long test time, low fault detection rate, high cost of testing problems.The results of this paper can be widely used in areas that require fast fault location, such as national defense military and industrial field and so on. Overall, the main research works of this paper are as follows:First, the D-Tent(Digital Tent,D-Tent) and D-PL(Digital Piecewise Linear,D-PL) Chaotic model ATPG(Automatic Test Pattern Generation, ATPG) were proposed to solve the shortcomings of fault detection rate of BIST. After parameter optimization and characteristics analysis of chaos, the chaotic models were used in experimental research of standard test circuit. This mothod was compared with othe ATPG of BIST to get the results and conclusions.On this basis, chaotic time series testing vectors were applied to the BIST of analog circuit. Finally, we use the value of the correlation between input chaotic time series and output time series as a fault signature, the simulation results show the feasibility of the method.A mothod was propose to solve the problem of analog circuit test pattern generation complexity of BIST, and overcome the shortcomings of the additional DAC circuits which increase the hardware area and the introduce testing error. This mothod uses square-wave as test pattern, which generated by its own. At the same time, the output response analysis of multi-dimensional fault feature extraction optimization was used. The mothod is introduced in analog BIST fault diction to prove the practicality and effectiveness.In order to evaluate the testability improvement degree of electronic systems, uniform evaluation system and indicators are required. On the basis of analysis advantages and disadvantages of existing testability modeling mothd in this paper, the testability modeling method which suit to electronic systems hierarchical was studied. This mothod can establish a systematic testability and analysis modeling respectively from the system and the basic component failures to guide design for test.To overcome the traditional test optimization easy to fall into local optimum, test critical function was introduced in the importance based Petri net global optimization test sequence search method. This mothod select the large amount of test information, according to the principles of testing costs. At the same time, based on correlation model, fault reasoning strategy and reasoning rules were studied to locate the fault and achieve the purpose of fault diagnosis.At last, a typical electronic system platform based on BIST was developed, which combine with previous research and presentation of research results. The proposed theory and methodology on the BIST were verified through this platform. The experimental results confirmed that BIST testability design is feasible and practical. The design is a practical reference to electronic systems BIST and fault diagnosis strategy.