Simulation Of The Electrical Performance And Failure Analysis On Ferroelectric Thin Film Devices

Ferroelectric gate field-effect transistor （FeFET）, as one type of ferroelectricrandom access memories （FeRAMs）, is currently regarded as one of the mostpotential next generation memories with clear advantages such as the simplestructure, non-volatility, low power consumption, nondestructive read-out operation,high endurance, high speed writing, high density, irradiation hardening andcompatible with integrated circuit （IC） process. In this Ph.D. dissertation, theadvance of the ferroelectric materials and ferroelectric memories are reviewed in theintroduction, including the classification and physics properties of the ferroelectricthin films, and the development history, current status and existing problems of theferroelectric memories. On this basis, the electrical performance and failuremechanism of the basic structures of FeFET, such as ferroelectric thin film capacitor,metal-ferroelectric-insulator-semiconductor （MFIS） structure and MFIS-FET, areinvestigated by combining the theoretical modeling and numerical analysis. Themain contents and results are given as follows.1. The combined model of Miller theory, thermionic emission and carrierdrift-diffusion is derived to simulate the leakage current density-voltage （J-V）characteristics through BST thin film capacitors. The influences of the donorconcentrations, space charges, film thickness and electrode materials on the currentdensities have been studied. We found that the simulated currents show thehysteresis and increase with the increasing donor concentrations and decreasing filmthickness. The influence of space charges at the cathode interface on the J-Vcharacteristics is apparent, whereas the influence of the space charges at the anodeinterface is negligible. The currents though Au/BST/Pt capacitors are larger thanthose though Pt/BST/Pt capacitors, which indicates that the higher the barrier heightis, the smaller the current densities are. All the simulation results show agreementwith the previous simulation and experimental results. The present research workmay be helpful to explain the fatigue mechanism and may provide some usefulguidelines to the design and performance improvement of BST thin film capacitorsand other BST thin film devices.2. Taking account of the field-dependent permittivity, J-V relationship isanalytically derived for space-charge-limited leakage currents （SCLC）, and it has been used to simulate the J-V characteristics of BST thin films. The influences of themobility, ferroelectric parameters, and film thickness on the leakage current densitieswere simulated and discussed as well. The results showed that J-V curves can bedivided into two regions: the low-field region with the slope1.99and the high-fieldregion with1.00. The high-field region starts at a nominal electric field108V/m,which corresponds to the experimental quasi-Ohmic region, indicating that thehigh-field quasi-Ohmic region may result from the field dependence of thepermittivity. Neither the slopes of J-V curves nor the transition voltages depend onthe carrier mobility. The leakage current can be influenced by the ferroelectricpolarization of high-K and ferroelectric thin films. At the same applied voltage, Jdrops with the increase of BST thin film thickness, which is consistent with theprevious experimental results, and both the slopes of J-V curves and the transitionelectric field do not depend on the film thickness.3. Considering the history-dependent electric field effect，we used the dipoleswitching theory （DST） to describe the polarization-electric field （P-E） relationshipof the ferroelectric thin film. Combining the DST with the silicon physics ofmetal-oxide-semiconductor （MOS） structure, an improved model was proposed todescribe the capacitance-voltage （C-V） characteristic and memory window of theMFIS structure. Using the model, the hysterisis loop and the thickness effects of theferroelectric and insulator layers on the C-V characteristic and the memory windowwere investigated and compared with the experiments for Pt/SBT/ZrO2/Si andPt/BLT/MgO/Si structures. All the simulation results show good agreement with theexperiments, verifying the validity of the model. This work may provide guidancefor the design, fabrication and performance improvement of MFIS structure bypredicting the C-V characteristic and memory window.4. A model is developed to investigate the interface effects on the C-Vcharacteristic, drain current-gate voltage （I_D-VGS） and drain current-drain voltage(I_D-V_DS) of MFIS-FETs. Two interfaces have been discussed including the interfacelayer between the ferroelectric and electrode and the SiO2layer between theinsulator and the semiconductor. The C-V and I_D-VGScharacteristics with fixedinterface layer and SiO2layer thicknesses modeled using the improved model areconsistent with the previous experiments, which verifies the validity of the improvedmodel and the existence of the interface layer or SiO2layer or both in theexperiments. The characteristics, such as C-V, I_D-VGSand I_D-V_DS, are then modeled respectively with various interface layer and SiO2layer thicknesses. We found thatthe existence of the interface layer and SiO2layer deteriorates the characteristics ofMFIS-FETs, and the thicker the layer is, the worse the characteristics are. Thememory windows of the C-V curves, the I_D-VGSand I_D-V_DScharacteristics modeledat interface layer thickness ratios0.00,0.05,0.10and0.15are similar to thosemodeled at SiO2layer thickness0.00,2.00,4.00and6.00nm respectively, indicatingthat both layers should be considered in the design, fabrication and measurement ofthe MFIS-FETs. Additionally, the interface layer and SiO2layer can be distinguishedby comparing the capacitance in the accumulation region. Therefore, this model canhelp the experimenters optimize their experimental processes.5. Combining the extended Preisach model and the DST respectively with theinterface model, mobility model and silicon physics, two improved models wereproposed to describe the electrical performance of MFIS-FET. To confirm thevalidity of the improved models, the simulations and comparisons were made asfollows.（1） The C-V characteristic of MFIS structures, I_D-VGSand I_D-V_DScharacteristics of MFIS-FETs were evaluated by the improved model based on theextended Preisach model and compared with those based on Lue model and theprevious experiment. The simulation results are more consistent with theexperiments than those based on Lue model.（2） The C-V characteristic of MFISstructures, I_D-VGSand I_D-V_DScharacteristics of MFIS-FETs were also simulated bythe improved model based on the DST. The results were compared with theexperiment, which show good agreement. The influence of the gate voltage, SiO2layer thickness, and interface layer thickness on the C-V, I_D-VGS, and I_D-V_DScharacteristics were simulated and the results showed that the memory windows ofC-V and I_D-VGScharacteristics, as well as the I_D-V_DScharacteristics, increase withincreasing gate voltage. The existence of the interface layer and SiO2layerdeteriorates the characteristics of MFIS-FETs, and the thicker the SiO2or interfacelayer, the worse the transistor characteristics, further demonstrating that they are thecause of the retention loss.