Improved Ge Condensation Technique And Its Bio-sensing Devices

Post 22 nm era, new device structures and new channel materials were used to solve the problem facing the traditional silicon CMOS. According to International Technology Roadmap for Semiconductors(ITRS), the channel material strain Si will be gradually replaced by Ge/III-V materials, as the semiconductor device scaled down to 15 nm. As a combination of the two benefits of Ge and SOI, high carrier mobility and CMOS compatible, germanium-on-insulator(GOI) is expected to be widely used as the channel material. In addition to be used in high speed CMOS devices, GOI has a better performance at III-V based high-speed photodetector and the solar cell.Ge condensation technique is one of the most versatile methods in the fabrication of ultrathin GOI substrates. However, due to the fact that the misfit dislocations(MDs) generated at SiGe/SOI interface in the temperature ramping up process gradually fragmented into thread dislocations(TDs), the threading dislocation density(TDD>107cm-2) in the final GOI product does not meet the substrate criteria for CMOS applications. Under the above backgrounds,combined with the key national project “Technology development of high mobility device based on new mixed crystal SOI and GOI”, the research work in this thesis mainly focuses on:1、The 8 inch GOI wafers were fabricated by improved Ge condensation technique. The testing results show that the obtained GOI wafer has high crystal quality with smooth surface morphology(RMS<1nm) and perfect monocrystalline structure. Using preferential etching technique and plan-view TEM tests, the threading dislocation density(TDD) of GOI obtained by the improved method is significantly reduced from 1×107 cm-2 to 7×105 cm-2, compared to the traditional Ge condensation approach. The dislocation formation mechanism was deeply studied. The fabrication process and analysis of materical performance were shown in the chapter two.2、The mobility characteristics of GOI material were studied through the performance of pseudo-MOSFET and S/D schottky barrier MOSFETs. We present the operation of 30nm-thick GOI pseudo-MOSFETs(Ψ-MOSFETs) fabricated by traditional and improved Ge condensation technique. The output characteristic shows an on-current is enhanced by a factor of 2 compared to the traditional GOI p-MOSFETs. In addition, a considerable enhancement(56%) of the holes mobility for the modified Ge condensation approach is achieved. When it comes to the schottky barrier GOI MOSFETs, the Ge device has obviously larger drain drivability than Si counterpart. The perparation of devices and the performance were shown in the third chapter.3、With the combination of Ge condensation technique and CMOS process,the Ge-SiO2 core-shell structure NWs and the back-gate GeNW-FET device were fabricated. After GeNWs were covalently modified with APTES, the nanosensor showed highly sensitive concentration-dependent electric current change in response to different pH value, Subsequently, GeNW based nanosensor revealed high sensitivity for rapid and reliable detection of target miRNA125 a, which was linear over a large dynamic range with a detection limit of 5 fM, and high specificity in one-base mismatched target DNA discrimination. The perparation of bio-sensing devices and the detection process were shown in the third chapter.