Research On Key Techniques Of Software-Defined Radio Receiver Chip For Industry Specialized Applications

Recently, the frequency band of industry specialized applications is scarcity, which can not meet the requirement of rapid growth of industry specialized, and communication technology of key industry is subject to foreign manufacturer. This thesis studies on key techniques of Software-Defined Radio(SDR) receiver chip for industry specialized applications, including reconfigurable, out-of-band blockers rejection, harmonic interferences rejection, calibration, low noise and high linearity RF front-end circuits, reconfigurable and low power analog circuits design techniques.The thesis studies on key techniques of interference-robust receiver, and proposes an out-of-band rejection receiver architecture, basing on out-of-band rejection low noise amplifier, voltage-mode passive mixer and current-mode low pass filter, which improves out-of-band blockers rejection. The thesis also presents a harmonic rejection calibration technique, the gain mismatch and phase mismatch can be calibrated with gain adjustment, which improves harmonic interferences rejection.The thesis studies on design techniques of low noise, high linearity and low power circuits. The thesis proposes a dual-feedback low noise amplifier improving out-of-band rejection and reducing noise figure. The thesis also presents two high performance operational amplifiers, which adopt nulling-resistor Miller feed-forward and active feed-forward techniques to improve the high frequency performance, and use Quasi-Floating Gate technique to improve the driving capability.The thesis studies on digitally assisted auto-calibration technique, and presents LC load resonant frequency calibration method of low noise amplifier, using down-conversion path of receiver to reduce the calibration complexity. The thesis proposes a piecewise linear power detector structure, which improves the detection sensitivity and dynamic range simultaneously.Basing on the proposed key techniques, the thesis designs two 0.1-5.0GHz SDR receiver chips for industry specialized applications with TSMC 65 nm CMOS process. The first chip adopts three parallel RF front-end paths to support various application, and features flexible reconfigurable architecture. The second chip, basing on 8 phase voltage-mode passive mixer architecture, can rejection out-of-band blockers and harmonic interferences at the same time.The testing results show that the SDR receiver achieves 100 dB maximum gain, 1.7dB noise figure, 16 d B noise figure with-5dBm out-of-band blocker and 20-76 mW power consumption. It achieves 71 dBm calibrated out-of-band IIP2, 58 dB calibrated image rejection, 61 dB and 68 dB calibrated 3rd-order and 5th-order harmonic rejection. The two SDR receiver chips can support DVB-H, LTE, 802.11 g and ZigBee popular communication standards, and the demodulation error vector magnitude of TD-LTE signal is 5%.