Design And Optimization Of Network-on-chip Based Many-core Systems

With the maturity of nanotechnology and chip integration techniques,as well as the development of the integrated circuit design methods,chip packaging and test techniques,the size of the transistors has become smaller,such that multiplied number of transistors are equipped on a single chip.Large-scale integrated circuits and Very Large Scale Integration(VLSI),are becoming the main direction for the development in embedded systems.On-chip many-core systems are widely used for VLSI design to satisfy the ever-growing demands of high-performance and low-power consumption in the design of embedded systems.Among the designs,Network-on-Chip(NoC)has been developed as the prevailing communication architecture for the next-generation of MPSoCs,providing ultra-powerful parallel processing capabilities,high-bandwidth on-chip data transfer,efficient computing,and high system scalability for interconnected multiprocessors.Although we can still pack more transistors per area on a chip,power density has been trending upwards since switching power per transistor is not scaling commensurately.Coupled with the physical limits imposed by device packaging and cooling technology on peak power density,consequently,silicon chips cannot be fully utilized.A large portion will be “dark” or “dim”,i.e.,either be powered-off or under-clocked,which rises Dark Silicon problem.Dark silicon enables systems to maintain systematic allowable power budget and safe temperature.However,it induces new design challenges in NoCs,such as contradiction between improving application performance,energy efficiency,and chip thermal reliability.Techniques have been developed to selectively activate non-adjacent cores to avoid chip temperature hotspot,while resulting in unexpected communication overhead due to the longer average distance between active cores,and in turn affecting application performance and energy efficiency,when NoC is used as a scalable communication subsystem.To this end,this thesis has proposed the design and optimization methods from three aspects: fine-grained optimization of on-chip communication to improve system performance,hardware-software co-design for high-performance and low-power in thermal reliable manycore systems,co-optimization of computation and communication for hybrid NoCs.Compared with existing work,this work has deeply studied the architectural characteristics,based on which hardware and software collaborated approaches are presented for achieving high performance and low power of heterogeneous multiprocessor system fine-tuned by system-level application mapping and scheduling techniques.The main contributions of this thesis are as follows:(1)Fine-grained optimization of on-chip communication has been made for NoCs.Finely consider network conflict in spatial and temporal dimensions,and model on-chip data transmission by Integer Linear Programming(ILP),to obtain the optimized communication efficiency and system performance-energy efficiency.(2)With the objectives to co-optimize system performance,power efficiency and chip thermal reliability in dark silicon manycore systems,three alternative hardware–software collaborated techniques are proposed with the matched strategies to collaboratively achieve optimization in different design phases and aspects.First,FoToNoC and QCNoC are proposed to balance chip thermal reliability and network communication performance.Matched software-based algorithms are correspondingly proposed for task mapping and scheduling.Combination of hardware/software co-design has achieved network communication efficiency and the performance-power efficiency,and effectively managed chip heat distribution to ensure chip thermal reliability.Furthermore,with single-cycle multi-hop data transmission enabled by SMART NoC,on-chip communication topology can be dynamically reconfigured by data exchange requirements,enabling network communication with less communication conflict,low latency and power consumption.(3)The approach of hardware-software co-design is proposed for accelerating computing and communication on NVM-based hybrid NoCs.For communication-and computation-intensive applications(e.g.,CNN),computation has been novelly offloaded to on-chip routers where data operation can be processed in NVM during transmission,such that communication latency is significantly reduced.Comprehensive experiments are conducted to evaluate the presented approaches based on existing simulators,including GEM 5,McPAT,HotSpot and MatEx.Experimental results by synthetic benchmarks and real-world applications show the effectiveness of the proposed approaches in improving application performance,chip temperature,and system energy efficiency for NoC-based MPSoCs.