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Study Of Structures And Dispatching Schemes For High Performance Three-stage Clos Switching Fabrics

Posted on:2015-05-01Degree:DoctorType:Dissertation
Country:ChinaCandidate:M S ZhangFull Text:PDF
GTID:1108330464968869Subject:Communication and Information System
Abstract/Summary:PDF Full Text Request
The Internet, which is based on the packet switching, plays a more and more important role in the present telecommunication network. With the rapid development of the optical transmission technology and optical transmission networks, the capacity and salability of current routers and switches cannot meet the future demand. On the other hand, packet switching is going to be used to carry other traffic, such as to replace the bent-pipe transfer mode in the satellite telecommunication, or to carry real-time voice which is commonly carried by the circuit switching. These will make some new demands on the complexity, throughput, delay and delay jitter of the switching fabric. The single-stage switching fabrics, such as crossbar switches, are deficient in capacity and scalability, thus they cannot be used to build large-capacity switching fabrics. The Clos switching fabric, which is built from small-capacity switching modules, is regarded as an attractive solution for the next-generation routers and switches due to their modularity, scalability and non-blocking property. The aforementioned new demands on the switching fabrics are studied in this dissertation based on the Clos switching fabric, and the main contributions are shown as follows.1. The throughput degradation in the memory-space-memory(MSM) Clos switching fabric is studied, and a divide-and-conquer dispatching scheme is proposed to achieve high throughput performance under a variety of traffic models. In the proposed dispatching scheme, the VOQs in the first stage are organized into several colliding fields, each of which corresponds to an output module. Then the dispatching problem in the MSM Clos switching fabric can be divided into a series of cell-selecting operations in each colliding fields. By adopting the serial matching strategy, the number of cells that may collide at each central module is reduced, followed by high throughput performance. Meanwhile, the number of round-robin arbiters and inter-stage links in the switching fabric is reduced, thus the hardware design can be simplified. Simulation shows that high throughput can be achieved under many traffic conditions, and a low average delay can be achieved as well.2. The time complexity of the dispatching schemes for MSM switching fabric is analyzed, then a pipeline-based dispatching scheme named reverse dispatchingscheme, and a line-grouping MSM(LGMSM) architecture which is able to lower the computation complexity are proposed.Different from the traditional dispatching schemes in which the matching is performed in the same order as the switching modules are arranged, the reversed dispatching scheme first distributes tokens among all the central modules in a predetermined round-robin fashion, in which the internal matching is performed independently. Then the matching results are sent back to the first stage to guide the forwarding of the subsequent cells. In the proposed reverse dispatching scheme, the distribution of the tokens doesn’t depend on the result of last matching, with which the pipeline-based dispatching scheme can be implemented. Meanwhile, the dispatching for the three-stage Clos switching fabric is simplified to the matching problems for the single-stage crossbar switches. Theoretical analysis proves that the reversed dispatching scheme is able to reduce the time to complete a scheduling without introducing additional hardware overhead.In the LGMSM architecture, the single link between a pair of switching modules is replaced with a group of parallel links, thus the number of arbiters and the size of each arbiter are reduced drastically when the capacity of the switching fabric is unchanged, which is followed by low computation complexity. Meanwhile, the memory speedup is eliminated in the LGMSM architecture by adopting multiple independent memories in the first- and third-stage modules in substitution for the shared memories which were commonly adopted. Simulation suggests that when the same dispatching scheme is adopted, higher throughput performance can be achieved in the LGMSM architectures than the original MSM switching fabric.3. The problem of forwarding both circuit and packet traffic over the same switching fabric is studied, and a combined circuit/packet switching fabric and the dispatching scheme with strict Qo S-guarantee are proposed, in which the internal links of the switching fabric are divided into quasi-static and dynamic links to forward the circuit and packet traffic respectively. The dispatching scheme sets up virtual paths for the circuit traffic to provide them with strict Qo S guarantee, and the remained bandwidth is used to provide the packet traffic with best-effort service. Both circuit and packet traffic are forwarded over the same switching fabric, meanwhile thecircuit traffic will not be blocked by the packet one. Simulation shows that the strict Qo S guarantee can be achieved for the circuit traffic in the proposed switching fabric, and high throughput can be achieved for the packet traffic simultaneously.4. The out-of-sequence problems in the space-memory-memory(SMM) and memorymemory-memory(MMM) Clos switching fabrics are studied, then the load-balanced Clos(LB-Clos) switching fabric and the cross-point buffered Clos(CPB-Clos) switching fabric are proposed in which in-order cell delivery is provided.In the LB-Clos switching fabric, two-stage load-balanced switches are adopted for each central module, then the connection pattern with the properties of staggered symmetric and a feedback-based dispatching scheme are employed independently. Cells of the same flow will experience the identical delay when passing through the second stage and arrive at their destination OM in order. Meanwhile, the overflow problems at the middle-stage buffers are avoided with the proposed dispatching scheme. Simulation shows that high throughput performance can be achieved under a variety of traffic models, and a low average delay can also be achieve especially when the traffic load is heavy.In the CPB-Clos switching fabric, the identical cross-point buffered crossbar switch is adopted in all the switching modules. Input modules first distribute cells of the same flow among all the central modules in a predetermined round-robin fashion, then the oldest-cell-first arbitration is adopted at each output port of the central stage. Finally output modules read out cells from each cross-point buffer in the same round-robin fashion. Theoretical analysis proves that the out-of-sequence problems can be avoided, meanwhile simulation suggests that high throughput performance and low average delay can be achieved simultaneously.
Keywords/Search Tags:Packet Switching, Three-Stage Clos Switching Fabric, Dispatching Scheme, Complexity, Quality of Service
PDF Full Text Request
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