Research On Swiching Structure And Scheduling Algorithm For Tree-stage Clos Networks

Taking the special on-board switch application environment into account, space qualified FPGA chips are used to implement the design of switching program. Due to the limited resources of space-on-chip (including logical resources and storage resources), only a cascade of multi-level multi-chip switching network architecture can be used to realize the switch with more ports. Currently, the research methods of multi-stage interconnection networks mostly concentrate on Clos networks and Banyan networks. Among them, three-stage Clos networks due to its modular strong, good scalability and the ability to achieve a strictly non-blocking switching within the network have been growing more popular.Based on the laboratory research project undertaken-’"Multi-stage switching programs and Simulation", a study of three-stage Clos networks are carried out in this thesis with the application background of on-board switch. Firstly, the current switching structures of Clos network are studied. Accoding to the requirement of onboard switch, the defects of these structures and algorithms are analyzed. Secondly, in order to solve the problems of the existing switching structures and scheduling algorithms of Clos network, two improved structures and algorithms are proposed.Simulation results show that the improved structures and algorithms perform better than the previous ones. Both of these structures and algorithms are easy to implement and have a high scalability, therefore, they are more suitable for on-board switch. Finally, to improve the network throughput, lower average packet delay and delay jitter, the output port forwarding mechanism to schedule slices as one unit is presented at the third stage Clos switching network module. The simulation shows that using the form of slice packet forwarding mechanism, the network performance has improved significantly when there are more short-packets in the network.