Design Of SDIO Host/Device Controller

The information network is developing towards ubiquitous network,wireless communication So C chip,compatible with protocols such as mobile communication,Bluetooth,GPS,WLAN and having the function of navigation positioning,large-scale self-organized wireless communication network,will be the core infrastructure of network construction in the future.Compared with USB interface and PCI/PCIE interface,the SDIO interface is relatively simple and can meet the requirements of low power consumption of mobile devices,so it has been widely used in SoC.A SDIO host/device controller is designed in this paper according to the actual demand of a SoC chip,which is compatible with a variety of communication protocols and used in ubiquitous network.The biggest characteristic is that it can operate in host mode and device mode,so as to be able to communicate with other hosts or devices flexibly.After studying protocols relative to SDIO and commonly used circuits in ASIC design,this paper designs the framework according to design requirements.All of the sub modules are divided into AHB clock domain unit,SD clock domain unit and cross clock domain unit according to their working clock domain.In AHB clock domain unit,this paper designs a universal register read and write timing for AHB slave interface,which is convenient for transplant and maintenance.A burst transmission strategy is also designed for the DMA configuration module in order to maximize the transmission speed.In SD clock domain unit,command state machine and data state machine are designed for host mode and device mode separately,so the controller can work in both host mode and device mode.In cross clock domain unit,a simple bidirectional asynchronous FIFO is designed based on the traditional FIFO.It adds a set of read and write pointers as well as a transmission direction control signal and finally realizes the function of bidirectional dada transmission.The Hardware/Software Co-Verification is used to verify the SDIO host/device controller.The virtual prototype is verified on Modelsim,and the FPGA prototype is verified on the DE4 development board manufactured by Terasic.The results show that the controller works well and meets the design requirements.The maximum operating frequency of the host mode is 40 MHz,the maximum read and write speeds are 14.922MB/s and 13.534MB/s.The maximum operating frequency of the device mode is 48 MHz,and the maximum read and write speeds are 17.548MB/s and 16.051MB/s.