Design And Verification Of High Speed SDIO Interface For WIFI Chip

WIFI technology occupies an important position in the field of wireless communications for its transmission speed,high stability,and low power consumption.With the development of science and technology,people's demand for WIFI chip tend to be more specific.Fast and efficient extension of WIFI chip peripheral functions is the great chal enge for developers currently.This paper focuses on a high-speed external expansion interface-SDIO interface.Integrating it on the WIFI chip architecture,it can not only provide high-speed transmission interface for WIFI chip,but also can expand the application function of WIFI chip easily and rapidly for its strong scalability.The main contents of this paper include : according to the functional requirements of the WIFI chip,SDIO interface register transfer level(RTL)hardware description is completed.As well as FPGA test,NC post simulation of RTL and chip test.The final purpose is not only to make the SDIO interface to support all the communication characteristics within specifications,but also improve the maximum clock frequency range of the SDIO interface,through the design of synchronous operation on the signals under the internal two clock domains.First,this paper introduces the overall architecture of the WIFI chip and the AMBA-AHB bus protocol of the architecture,including the bus interface and the important transmis s io n timing.Then the paper describes the protocol of SDIO interface,including the description of SDIO card interface and SDIO command,response,data format and transmission timing.Then the Verilog HDL is used to complete the design of the SDIO interface register level according to the design requirements and standard protocol specification.Finally,the function and realization of each module is described in detail.Secondly,the SDIO host simulation model is designed,the simulation platform is built,and the simulation of the designed RTL is carried out.Using the Xilinx Inc.ZC706-ZYNQ series development board do FPGA testing that is completed to check the SDIO interface's timing,while finishing the SDIO interface transmission speed and compatibility verification.At last,using the constraint files and process library provided by FPGA test to generate the SDF file,while turning RTL into a netlist file for NC post simulation.Finally,the chip taped out by SMIC 55 nm COMS process,packaged by QFN technology,and masked marking on PCB.Then,the SPI mode of SDIO interface is verified by the SPI IP on WIFI chip,and the SD mode of SDIO interface is verified by the STM32.So the chip test is finally finished.The final chip test results show that the SDIO interface module design is reasonable and can meet the application requirements.The highest stable operating clock can reach to 70 MHz,the highest data rate can reach to 280 Mbps in SD4 mode.