Hardware/Software Co-verification Solution Based On FPGA And ISS

With the rapid development of IC manufacturing technology. SoC has emerged, which is a highly integrated single-chip embedded system. Currently. SoC has become the international development trend of VLSI(very large scale integration, VLSI), leading the development of embedded systems.In order to meet SoC's highly integrated features, high-performance requirements, as well as the high level of design and silicon costs, designers must ensure that the system functions are correct before they design its layout, wire and tape. However, it is very difficult to verify such complex SoC. Moreover, with the continuous improvement of integrated, SoC will be more difficult to verify. The technology of verification has got behind comparing with the design technology. It is regarded as bottleneck of designing VLSI that verifying the final design is correct.Software and hardware are separated to verify in traditional method of verification, which means that it is only for hardware verification during the cycle of hardware designing, the software must wait after a good hardware platform built. This paper establishes a hardware-software co-verification platform for embedded system, which is based on fast prototyping FPGA and instruction set simulator ISS, and carries out a in-depth exploration and study. First, the program model is separated to three stages based on function. The level model is clear. Second, For this method of achieving, this paper designs and transforms the traditional ISS for adapting to co-verification environment, and designs the modified algorithms of ISS core scheduling and simulation of register's loading commands Third, this paper analyses the co-verification process of interactive between software and hardware, and gives the structure of BFM and its detailed work processes, and implements the algorithm of bus timing generating. Fourth, this paper analyses and discusses the co-synchronization problem in the process of software and hardware, and designs to achieve its co-synchronization algorithm. Fifth, this paper designs and implements a way to the verification environment based on Monitor and Host.As an example of that the co-verification solution based on FPGA and ISS takes a clear advantage compared with several other commonly used verification system for embedded applications.