Research Of SDIO UVM Verification IP Technology

With the rapid development of integrated circuit and the promotion of chip complexity, the role of verification played in chip design is more and more important. In order to accelerate the time-to-market, there is a need to improve the speed and efficiency of verification, thus the higher requirements for verification techniques and methods has been proposed. The UVM provides a clear, unified industry-proven validation standard that has many advantages which traditional validation methods can not achieved,especially its reusability can accelerate the build process of the verification platform.SoC design need to use a large amount of IP cores. Verification IP can be used in SoC system-level verification as it can reduce the workload of verification engineer and accelerate the verifiaction process. SDIO is widely used in consumer electronics,providing high-speed, low-power data storage and application for mobile devices.On the basis of research and analysis of UVM technology and SDIO standard protocol, a bus function model which conforms with the SDIO standard protocol has been designed. By using UVM technology, SDIO verification IP and verification platform has been built. Various components used in this platform are implemented,and a coverage model has been built to statistics and collection coverage. Finally, three test cases for this verification IP which is random test, basic test and error test have been designed based on coverage-driven verification. Then a self-test has been executed on the SDIO verification IP by using this test cases and 100% functional coverage has been reached. The results shown that the correctness of the designed verification IP and it can be used to verify a SoC chip with SDIO interface.