Research And Design Of SDIO Host Controller Based On GALS

The communication between SDIO host and SDIO device is complicated. It is time-consuming and low-efficient to be implemented by software. Therefore, every SDIO device needs a special host controller to deal with this problem. This paper presents some problems and solutions of the design about SDIO host controller.Globally synchronous designs are hardly applied to high frequency, high performance VLSI circuits due to some problems. Asynchronous circuits demonstrate advantages on low power and high speed, but lack of EDA tools supporting. Thus, GALS circuits, which take the advantages of both technologies, is becoming popular. The idea of GALS is that encapsulate all the modules, which is designed with synchronous circuits, with synchronous/asynchronous interfaces. There are multiple clock domains in the design, so GALS is used. We present a handshake circuit with standard cells based on the analysis of 4-phase handshake protocol to deal with the problems of signals handshaking and metastability.Because the SD protocol is based on command and data stream, the interrupt delay may be introduced. The circuit of ADMA, which is controlled by a state machine, aiming at this problem, is presented in this paper. The key of AMBA, which used in our design, is the arbitration of the bus. We discuss the algorithm usually used in arbitration, and present a multiple dynamic algorithm with better performance.Based on the research and analysis of functions and architecture of SDIO host controller, we present a front-end design of SDIO host controller and verification methodology with Top-Down design topology. This design is described with Verilog HDL. The functional verification and static timing analysis are performed by using EDA tools. The results show that the proposed design can meet the requirements of the system.