Research And Realization Of The Functional Verification For High Flux I/O Communication Protocol Stack

In order to solve the bus problem during the process of the computer system development, and satisfy the requirement of the external devices for the bus bandwidth, Intel put forwords the third generation of bus technology: PCI Express(hereinafter referred to as the PCIE). The study of PCIE equipment agreement is leaded to the vigorous development with its distinct technology advantages and broad application prospects in terms of the equipment Internet and data interaction. Therefore, the verification of PCIE has become an important part of function verification for SoC.At present, there are two kinds of integrated circuit function verification method: formal verification based on the form calculation and simulation verification based on the simulation running. Formal verification cannot gain the favor in industry because of its own inherent problems, even it is much more compliant with the goal of the verification, but the simulation verification has being widely used from its easy implement on the EDA tools. However, it cannot be denied that the development of simulation verification can’t keep up with the pace of the development of IC design. In recent years, all kinds of advanced verification technology and methodology have been created in order to reduce the gap which is gradually enlarged between the size and functional complexity of IC chip and functional verification technology development.Added network layer, set multiple data links into data link layer for link establishment with each blade link protocol to streamline and extension, the protocol stack chip which can be considered as the experiment of the paper verification platform is completed on the extension and improvement of the standard PCIE protocol bus hierarchy. This kind of design makes the protocol stack chip itself containing routing selecting function of Switch equipment, which also improves the data transmission speed. Although the protocol stack is made with our own custom communication protocol, which is different from the standard PCIE protocol specification, but the connection between protocol stack and peripheral equipment is still following PCIE protocol specification. Because the protocol stack work belongs to innovative project cooperated from the enterprises and scientific research units, there is not mature verification tools-including PCIE equipment testing suite in market. This paper designs and implements a functional verification environment coded with the System Verilog language and driven by the combination both vector state diagram and coverage. With strategy of variable weights constrainted Random Stimulus Generation(CRSG, Constrainted Random Stimulus Generation), we use the platform product a comprehensive functional verification of RTL codes.First, this paper illustrates appearance of the System Verilog language and its methodology, and introduces various verification technology of the System Verilog language which can improve the verification efficiency in the process of constructing of the AISC functional verification platform at the same time. In addition, this paper gives a simple instruction to the organizational structure of the simulation verification platform based on the System Verilog language.Second, in this paper, we gives a simple analysis and instruction to the storage TLP data packet with the PCIE specification, as well as the internal structure and working principle of communication protocol stack equipment which is based on PCIE protocol interface. At the same time, topology of the data center network is described, where the role of protocol is emphatically introduced in this paper.Last, we build a simulation verification platform according to the functional requirements of the communication protocol stack, with the configurable extension, completion data comparison and variable weight CRSG. In this paper, we introduced the Verification platform architecture and the workflow of various functional modules in detail, including the Generator, Driver, Monitor, and Scoreboard. We also have completed the function verification of communication protocol stack with the platform’s work. The verification reports and coverage data show that the platform has already completed the protocol stack verification work. Andthe project has been passed the acceptance of the cooperation company in November 2014.