Research Of Functional Verification Based On Systemverilog

Along with the increasing of the scale and complexity of Integrated Circuits, the functional verification of Integrated Circuits becomes more and more difficult. Simulation verification and formal verification are two techniques of functional verification. By far simulation is the primary verification, but simulation has some problems. It is not convenient to build verification environment and test-case and to find the place where bug occurred; The progress and completeness of functional verification are hard to measure.In order to solve these problems, this dissertation builds hierarchy verification environment based SystemVerilog in the packet processing and forwarding chip. The hierarchy verification architecture enhances the reusability of components in verification environment and the efficiency of building verification environment. With the constrained-random technique of SystemVerilog, the number of constrained-random test-case is decreased to a quarter of direct test-case.Assertion Based Verification inserts SystemVerilog assertion into the design. Assertion improves the observability of design and it is convenience to debug with the help of simulation log.This dissertation introduces functional coverage and assertion coverage based on code coverage and uses Coverage Driven Verification to drive and measure the work of verification. In the verification of packet processing and forwarding chip, the functional coverage is 100%, assertion coverage is 100%, code coverage is 98.41% (line coverage is 99.26%, FSM coverage is 100%, condition coverage is 95.99%). It is effective to guarantee the completeness of verification with these three coverages.With the practice of verification work of packet processing and forwarding chip, this dissertation improves the simulation verification and enhances the efficiency and quality of verification.