Modeling Of Memory Resources Management And Optimizing Of Memory Bandwidth Management In Chip Multi-processor

Chip Multi-Processor(CMP) has become the mainstream and the development direction of the microprocessor. In Chip Multi-Processor, besides the "Memory Wall", the limited memory bandwidth, the memory resources contention among multiple cores and various program behaviors are challenging the memory subsystem design in CMP. How to effectively manage memory resources in Chip Multi-Processor to improve processor performance has been widely researched. In order to better analyze and optimize the Chip Multi-Processor memory resources management, we need to model, to build a corresponding software simulation platform. In addition, in the Chip Multi-Processor, the limited memory bandwidth has become the bottleneck of performance improvement, and we need to schedule memory access requests to improve utilization of the memory bandwidth.In this paper, the memory resources management in Chip Multi-Processor is modeling to provide an effective analyzing and evaluating method for CMP memory resources. Based on this, a management policy for an important shared memory resource in CMP, memory bandwidth, is proposed, which is called prefetch-aware memory access scheduling. In this paper, the main work includes:1. Modeling of Chip Multi-Processor memory resources management. Based on the analysis and comparison of the current processor simulators, a CMP simulator called Gem5-M is designed and realized. Gem5-M simulator is the integration of Gem5 simulator and DRAMSim2 simulator, which can simulate the memory behavior in detail, making up the defects of Gem5 simulator that cannot truly simulate the Chip Multi-Processor memory system.2. Evaluating of Gem5-M. By using SPEC CPU2000 testbenches, and being compared with Gme5 simulator, Gem5-M is evaluated in the simulation speed and simulation precision. For the presence of DRAMSim2 simulator, Gem5-M simulator can better simulate the memory system, and the simulation precision is improved without obvious reduction in the simulation speed.3. Optimizing of memory bandwidth management. Due to the interference of useless prefetch requests, the performance of some applications could be decreased compared with the performance without prefetching mechanism.. On the basis of this observation, a prefetch-aware memory access scheduling policy is proposed. In this policy, demand requests are prioritized over prefetch requests, and the prefetch requests outstanding in the memory request buffer for longer than a threshold will be dropped to reduce the interference of useless prefetch requests. Gem5-M simulator simulates this policy, and the results show that it can improve the processor performance.