Adaptation And Error Analysis Of The Gem5 Simulator For Boom Processor

The RISC-V instruction set architecture is a new open source reduced instruction set architecture.It has a complete tool chain,supports a wide range of software,and has a good performance in high performance and low power computing.At the same time that the RISC-V instruction set was proposed,the University of California,Berkeley also designed the Boom processor based on the instruction set and opened the processor design platform.Boom processor hardware description code for actual processor production and official simulator for evaluating processor performance characteristics can be generated by the platform.However,the Boom official simulator simulation takes a long time and it is not possible to provide a complete simulation plug-in like a traditional simulator such as Gem5.Therefore,adapting the simulator of the Boom processor on the Gem5 platform is of great significance for the design space exploration of the RISC-V instruction set processor.This thesis analyzes the parameters of total performance and micro-architecture performance of Gem5 and Boom processors.The source of the Gem5 simulator error is analyzed in detail and the parameters are adapted.Based on the analysis of the work process of the main modules in the Boom processor pipeline,the main reasons of performance differences between Boom and Gem5 are analyzed in detail.After the key modules of the Boom processor design platform source code were analyzed,some major problems in the software platform were discovered and explored.Then some code is added to the Boom processor design platform to obtain the number of branch prediction failure events and the number of cache miss events for subsequent adaptation work.When the Boom and the Gem5 simulator run the same benchmark,the microarchitecture-independent parameters are inconsistent due to the implementation differences of the simulator system call mechanism.The problem is solved by modifying the Boom processor design platform code during the adaptation process.In the case where the parameters of the Gem5 and Boom processors can be matched as much as possible,the adaptation of the basic structural parameters is achieved.The computationally intensive benchmark was selected and tested on the Gem5 and Boom simulators.The results show that the average relative error of CPI(Clock Cycle Per Instruction,CPI)is reduced by 16.2% while keeping the structural parameters of Gem5 and Boom simulators basically the same.