| In the whole process of SoC design, memory system has become one of primary bottlenecks of system performance, which directly affects the overall performance of SoC. Only the average memory latency and bandwidth can be obtained from the hardware development board. However, the internal working states of the memory controller can not be gotten, which makes studying and evaluating the memory system in the purpose of finding out bottlenecks and optimizations a big problem. On contrast, by using cycle-accurate functional models, designers can obtain all the performance details in microarchitecture level. Although DRAMSim2 is a cycle accurate memory system simulator, it still has some errors in the address mapping, command scheduling, timing parameters and so on, which lead to unreliable results. Therefore, it is of great significance to optimize and adapt the DRAMSim2 model to improve its accuracy.The goal of this thesis is to adapt and retune DRAMSim2 to the real memory system of Odroid-U3. In this thesis, we use the memory trace stream generated by the full functional system simulator Gem5 as the input of DRAMSim2. In order to reduce the error caused by the memory trace stream, the CPU and Cache pails of Gem5 are firstly configured to be as similar as possible to that of Odroid-U3. The error sources from the bus interface, the command scheduling module and the memory physical interface have been analyzed by using errors between DRAMSim2 and the Odroid-U3 memory system. On one hand this thesis modifies the depth of memory access queue for the bus interface and formulas of memory access protocol for memory physical interface, on the other hand this thesis establishes the address mapping mechanism and FR-FCFS scheduling model for command scheduling module.Compared to the original DRAMSim2 model, the average memory access latency error of our model has been dropped from 40.5% to 12.5%; while the average memory access bandwidth error has been dropped from 21% to 8.33%. |
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