Design And Implementation Of An Instruction Set Simulator For RICS Processor

CPU complexity increases significantly due to the enhancement of Integrated Circuits(IC) integrity. It leads to the great importance of developing a high speed, flexibly configurable simulator.This thesis have designed and implemented an instruction set simulator orienting the classical RISC processors. The simulator is execution-driven and developed based on the Gem5 simulation platform. We optimize the instruction interpretation process on the basis of interpretation simulators and implementing types of instructions, including Load/Store, Data Process, Branch, Exception Generating and System Instructions. Thereafter, the memory system is also modeled, thus, the simulator is capable of running a variety of benchmarks, such as SPEC CPU200. The simulator features modularization in structure, configurable parameter, high flexibility and extensibility as a result of Object-Oriented-Program(OOP) language.This thesis makes the following contributions:1. RISC Instruction set simulation implementation and speedup. This thesis has functionally simulated 297 instructions in the RISC instructions set. We effectively implement system calls which are transferred to be executed by the host instead. In order to speed up simulations, this thesis optimizes the instruction process interpretation process by inserting interpretation information in the cache, which avoids instruction reinterpretation. Test results demonstrate that such optimization increases the simulation speed.2. Memory simulation and optimization. The simulator maps the address space of the target machine to the address space of the host machine by addressing mapping. In this way, the simulator can model the target machine memory using a continuous virtual memory space in the host machine. We build a global soft TLB table, which reduces the addressing time and enhances the simulation speed.3. Simulator test. The single-instruction test and the overall test show that, the simulator function is correct. Also, the simulator speed with instruction interpretation optimization and memory simulation optimization are enhanced by about 6.50% and 0.95%, respectively. Finally, with both optimizations, the simulator speed is enhanced by 6.76% around.