The Research And Implementation Of Memory Access System On Innovation DSP Chip

As the mainstream technology of the next generation wireless communication system, SDR(software defined radio) is a promising solution of wireless communication basestation process platform. One of the key issues in using software radio technology to realize baseband calculation for LTE protocol is the design of digital signal processing system As a important part of digital signal processing, memory system affects the success of digital signal processing system significantly. FT-Matrix DSP is a high-performance digital signal processor that executes the process of physical layer of LTE protocol, which has an independent vector processing unit and scalar processing unit. It can processes vector instructions and scalar instructions in parallel. The vector processing unit supports 16 vector instructions. Based on the FT-Matrix DSP architecture, we research kernel operation andalgorithm procedures of LTE protocol baseband processing. After the analysis of data demand of LTE protocol basestation system, we design the memory access system. According to the feature of memory acesss system, the memory aceess instruction set, scalar access system and vectror access system. Finaly, simulation is adopted to verify the function of the design and optimization.This paper focuses on the designs of memory access instruction set, scalar access system and vector access system. Memory access instructin contains the design of instruction format, instruction function and address access mode. Scalar access system includes the design of memory controller, memory bank and DCache, where a novel algorithm is implemented in DCahce to improve the hit rate and reduce the cost of miss. The vector access is comprised of the design of memory bank and memory controller.By developing an efficient and self-contained testbench, we simulate the design on both module level and system level. The result shows the correctness of this design. At the end of this paper, we discuss the synthesis of the memory access system.The synthesis results show that the the unit's clock frequency are 500MHz in 65nm CMOS technology, which is consist with our expection.