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The Design And Implementation Of SD UHS-Ⅱ Card Controller Base On FPGA

Posted on:2015-09-27Degree:MasterType:Thesis
Country:ChinaCandidate:Y J WangFull Text:PDF
GTID:2298330452950104Subject:Communication and Information System
Abstract/Summary:PDF Full Text Request
SD memory cards are widely used in digital products and have become a majormemory card standard. SD card host controller is a necessary part for SD cardapplication, widely integrated in mobile multimedia device. SD card host controllerconstantly upgrading with SD card, research on SD card host controller is with highvalue. In this paper, the design and implementation of SD card host controller arebased on FPGA, complying with SD4.0standard specification and supportinghigh-speed UHS-II card and meeting the requirements of high-speed transmissionwhich can be used in high-definition digital domain. And the design can be integratedby the IC backend sector to ASIC chips which can be put on the market.This paper introduces the latest protocol of SD card and SD card host controller,the SD card host controller top structure is divided and describes the function of eachmodule, design the SD control module, SD clock control module and the samplingclock selection module, finished functional simulation of each module. Finally, theentire design is test and verified on FPGA development board.SD control module is actually a direct communication interface between the hostcontroller and the SD card which control the transmission of command, response anddata. Reasonable state machine designed to control commands and responses and datatransmission between the host controller and the SD card. The CRC method used toensure the transmission of commands and data signals correctly. Clock control logicmodule provides SD host controller and SD card section the clock signal. DCM isused to provide a variable clock signal, and take advantage of the dynamicallyconfigurable function, variable clock frequency can be provided in flexible, dynamicadjusted mode. When the SD card is working in high-speed mode, it needed to findthe optimum sampling clock to sample data correctly. By designing the samplingclock tuning module and reasonable state machine to test the sampling clock phasesthat covering whole clock interval, and eventually to find the optimal sampling clock.Finally, the whole design are verified and tested on FPGA board to verify the basicfunction in application scenarios and performance of reading and writing on differentoperating mode. In this paper, the final design and implementation of the SD card controllersupports all kinds of new and old standard SD card. Read and write speeds of ToshibaUHS-II card is up to258MB/s,231MB/s. Read and write speed of ordinary SDcards also meet the requirements. Research work of this paper is carried out in WuhanO2Micro Electronics Ltd and is a part of the commercial project. The products ofcommercial projects have been available.
Keywords/Search Tags:FPGA, SD Host Controller, Sampling Clock
PDF Full Text Request
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