The Design And Implementation Of Embedded USB2.0 Host Controller IP Core

Firstly, this paper discusses the generation and development of USB (Universal Serial Bus), and the research status of embedded USB host controller in the world. Secondly, this paper describes USB2.0 protocol briefly, including USB architecture, physical interface, structure of packet in data transfers and the four types of data transfers.In the following, this paper discusses the design proposal of our embedded USB host controller, describes the structure and the design of function modules in detail, and the application of embedded USB host controller in electronic system is also described briefly. In our design, embedded USB host controller IP core supports high speed transfers and fast speed transfers, and it doesn't support low speed transfers. And the embedded USB host controller IP core implements four types of data transfers, which are control transfers, bulk transfers, isochronous transfers and interrupt transfers. In our design, a DMA master/slave controller is embedded whose work mode can be selected by setting the bits of registers accordingly by software. When there is not DMA master controller outside of the USB host controller, then the DMA controller in USB host controller works in master mode to exchange the data between transmissions / receive buffer and memory in system. When there is a DMA master controller, then the DMA controller in USB host controller works in slave mode. This design of DMA controller improves the flexibility of USB host controller and the speed of data transfers greatly. Meanwhile, the buffer is designed as ping-pong buffer. The design makes the data synchronization between CPU and USB host controller easier.This paper also describes the software system architecture of USB host controller, and the implementation of USB host controller driver is described in detail.Lastly, this paper describes the simulation and verification platform of embedded USB host controller, and describes the implementation of bus enumeration and data transfers on the platform, and the simulation result is analyzed. After FPGA verification and tapped out with 0.18 um process of Silterra corporation by MPW mode, we have tested the functions of chips come back.