The Design Of Host-FTL SSD Controller Based On FPGA

Due to the inherent defects of flash memory,solid-state storage devices requires a host controller and flash translation layer to solve two major conflicts: the contradiction between the limited erasing life of flash memory and the expectation of longer use time and the contradiction between insufficient single-bandwidth of flash memory and exponential growth in data throughput.This paper systematically describes a hybrid architecture based on FPGA logic and embedded processor implementation.Considering the design requirements of large bandwidth,FPGA hardware acceleration is utilized,and for load situations with changing demands the Host-FTL is applied.By separating the storage device from the flash translation layer,the host is allowed to manage the flash channel using the commands and message units provided by the system.The multi-level caching strategy and the command flow processing stabilize the lowest intra-disk delay at 20?s.The design of Host-FTL not only implements common software algorithms such as address mapping,wear leveling,and bad block management.By analyzing the bandwidth bottleneck of the system,ordinary writes uses the pipeline strategy and the parallel page group strategy for large file writes.Channel-level RAID arrays enhance data security,and regional wear balance increases the amount of write data to the SSD array.Finally,the performance of the system under different queue depths,number of threads,block size,and read/write ratio is analyzed and compared,and the actual test results are displayed.Compared with the ordinary SSD,the bandwidth of the system is increased by 20%~30%,and the number of instruction operations per second is 1.5~2 times,completed the design index.