Design And Implementation Of FPGA-based Time-to-Digital Converter With Shifted Clock Sampling Technique

Time interval measurement has always been an important research topic, it is also a kind of highly important means for recognition and detection, not only in the research field of sophisticated science foundation, but also in some application research and national defense construction.Time interval measurement mainly depends on the TDC(Time to Digital Converter) technology to realize. Compared with foreign microelectronics technology, our special integrated circuit(ASIC) and programmable logic devices such as FPGA technology is not mature yet. At present, most of the domestic TDC circuit designs basically rely on FPGA and can achieve PS level precision at the expense of the resource. So it has great practical significance to study the technology of less resource occupation, low cost and high stability of TDC technology.In this thesis, the analog and digital time interval measuring method were respectively introduced and analyzed, and in-depth study the circuit design and implementation of TDC using multi-phase clock sampling method in FPGA. The scheme does not need to construct the delay chains structure which occupy a lot of resources, only to generate a series of fixed phase shifted clock signals. The circuit system has a simple structure of less resource consumption, higher stability and easier to be implemented. The design is implemented on the hardware platform of Xilinx company production Virtex-5 ML507 development kit, and includes five modules: the clock generation unit, coarse counting unit, fine counting unit, a storage unit and a data transmission unit, these modules were written by VHDL language in the software development environment ISE14.7 and combined with Modelsim for software realization and simulation.Finally the test platform was built to verify performance of TDC with multi-phase clock sampling method. After several tests, the data results show that the TDC's time interval measurement resolution reaches 156 ps, precision is better than 66 ps, DNL and INL is less than 0.3LSB and 0.6LSB, respectively. Each of slices registers and LUTs and storage resources consumption is less than 2%. The TDC circuit has a good measurement resolution, high stability, low resources consumption, good practical value and application prospect.