Design And Implementation Of Digital Photo Frame Based On Qsys

With the development of consumer electronics, paper photo gradually replaced by the digital photos which become the first choice of record pictures. Digital Photo Frame is a kind of consumer electronic products used specifically to display digital photos.This subject takes FPGA of Altera Corporation as system hardware core, with its powerful EDA development tools, to build the Digital Photo Frame system Qsys system on the Avalon bus as the connection between FPGA hardware logic and software application.The design of the hardware circuit is the foundation of making actual Digital Photo Frame. This paper gives the designs of main circuit, which include power circuit, FPGA reset circuit, FPGA clock circuit, FPGA configuration circuit, DDR2SDRAM circuit, SDRAM circuit, SD Card interface circuit, and LCD interface circuit.This subject build the Qsys system through the Avalon bus to add and connect components which include Nios II processor, DDR2SDRAM Controller IP core, SD Card Controller IP core, SG-DMA Controller IP core and Video Sync Generator etc., The instantiating Qsys system is the main of FPGA hardware logic of Digital Photo Frame system.The main principle of the Digital Photo Frame system is:Nios II processor reads the BMP bitmap pixel data on the SD card through the FAT16file system, and stores the BMP bitmap pixel data on the DDR2SDRAM memory. The SG-DMA controller is initialized by the Nios Ⅱ processor. The SG-DMA controller read the BMP bitmap pixel data from the DDR2SDRAM memory before sent it to the Qsys system image processing channel. Finally, the image processing hardware automatically generates the corresponding RGB pixel data and synchronous timing.This subject entity is stable, reliable, clear, gentle, and flicker-free after debugging. At the last, this paper introduces the progress and prospect of the extend work of the project.