FPGA Implementation Of A Novel Parallel Turbo Encoder/Decoder

Reliable communications require error-free information transmission between source and sink, thus requesting good error-correcting capability in communication systems, such as the use of error control coding. After the Shannon limit was introduced, many codes had been proposed, such as Hamming Codes, BCH Codes and RS Codes, as well as Turbo Codes. The invention of Turbo codes is in fact a milestone in error-correting codes for their excellent error-correcting performance.However, the merit of Turbo codes is offested by their high decoding latency in many applications. This problem could be mitigated by employing parallel decoding. This thesis presents an FPGA implementation of a novel parallel turbo decoding algorithm based on frame split and trellis termination. In addition, a technique for resolving parallel memory access conflict resulted from parallel Turbo code is proposed.In this thesis, based on FPGA implementation, with clock frequency 33M Hz, 4 parallel sub-decoders, 4 times iteration and frame length of 1024, a desirable decoding throughout of 8. 3M b/s and 124us delay is achieved. Besides, an FPGA system board is also designed by using with EP2C35, which provides MAC/PHY and PCI interface for high speed communications. The test results indicate that the system board is effective and reliable.This thesis consists of five chapters. The first chapter introduces background of Turbo codes and related implementation technology. The second chapter presents encoder and decoder RTL design, as well as parallel interleaver/deinterleaver design based on multi-port memory. The SOC system based on NIOS Processor and uC/OS-II built on NIOS is discussed in the third chapter. The fourth chapter describes the work related to system design, test and debug. The last chapter concludes the thesis and presents some remarks on the future work.