Funcational Verification Of Multifunction Vehicle Bus Controllor

With the combination of computer networks and embedded systems control technology, the train communication network is applied to modern light rail vehicles and high-speed trains to connect vehicle. The International Electrotechnical Commission (IEC) has drawn up the train communication network standards named IEC61375-1 that specify the contents about Multifunctional Vehicle Bus (MVB) and Wire Train Bus (WTB), etc. In the process of our country self-research on high-speed train communication network control system, the functional verification technology plays an important role to ensure the compatibility, stability and reliability of chip used in train communication network controller. For the lack of observability and controlling, poor reusability of verification environment, not locating design faults immediately in the verification process, the traditional verification methods cannot meet the needs of Very Large Scale Integrated Circuit design nowadays. This thesis presents MVBC multiple functional verification, researches VMM verification methodologies deeply, and it unify assert verification, with binding of random testing and functional coverage to such verification method, for improvement the efficiency and completeness of verification.Firstly, this thesis presents the MVB bus norms and function definition, extracting the verification Requirements and function points definition of MVBC, making appropriate verification methods respectively according to the characteristics of the module level and system level verification. Secondly, for the disadvantage of traditional directional stimuli test, such as high workload and slow convergence, this thesis puts forward a method that combines the random stimuli and directional stimuli, and improves the test hit rate of corner case and uncover field by adding constraint to the random stimuli. Thirdly, this thesis researches on verification technologies based on assertion, by adding the assertion checkers in the design interface unit and internal logic unit, to find and locate errors in design quickly. Coverage is the main index to judge verification progress and design reliability. This thesis analyzes the classification and modeling of function coverage. With the coverage statistic, the random constraint vector is modified and the verification convergence process is accelerated. Based on the VMM verification platform, this thesis proposes a hierarchical, combining various verification technologies, high reusable, high automation and dynamic functional verification platform, has completed the module level and system level MVBC verification, and gives the bugs statistics reports and coverage analysis report.