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Research On Assertion Based Functional Verification For Boot Process

Posted on:2016-07-26Degree:MasterType:Thesis
Country:ChinaCandidate:L Y ZhaoFull Text:PDF
GTID:2308330464468972Subject:Software engineering
Abstract/Summary:PDF Full Text Request
Among the current integrated circuit chip development process, functional verification has become the part which costs the largest time scale. Limited to its lackness of observability and controllability, traditional functional verification methods are hard to locate design errors accurately and quickly. In addition, the long verification cycle, poor reusability and large workload of tradition verification make practitioners committed to seeking an optimization approach to improve the situation. Based on analysis for the characteristics of the traditional validation process, we propose a verification method based on the assertion--ABV, this verification approach is a new trend of the development of current verification methodology.With using ABV(Assertion-Based Verification) in verification process, we can improve the operability. Besides, early intervention of the design cycle can make those design flaws be found much earlier and let the cost of correcting defects reduce. At the same time, the assertion module can be implemented separately with design, make the assertion has a good reusability, the effect in improving efficiency for verifying is obvious.First paper proposed research articles–the Research on Assertion based Functional Verification for Boot process. The main contents focused on the specific achieve process and application of functional verification in IC design, background from the development of Xi’an Intel Mobile Communication Technology Co. XGOLD cellular baseband communications chip project. Take chip Boot process as a starting point, indicating that implemente process of SVA based functional verification method in the mobile phone chip. Proposed a method to improve verification quality, improve the efficiency of validation based on traditional simulation method, to better solve the verification problem encountered on the project.This paper describes the current difficulties faced by validation, analyze and compare the advantages and disadvantages of several major functional verification methods and introduce the assertion based verification method in a targeted manner. Then explan the details of assertions implementation process. Based on the introduction and summary of communications chip Boot functions and the Boot verification strategies, we completethe assertion insert point induction and extraction; At the last, set up the verification environment and complete the establishment of assertion module by extracting SVA design attributes.In the last part of the article we give the explanation about the validation results, analyze the role in an actual project which asserts play combine with research data. Summry the positive effects of assertion language in improving the verification quality and verification time. On the basis of the summary the full text, have a discussion about the main points of subsequent issues.
Keywords/Search Tags:functional verification, SVA, assertion verification, reusability
PDF Full Text Request
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