The Research And Inplementation Of Coverage Driven Verification

In modern IC design, the scale and complexity of chips increase exponentially.To assure the functional integrity of designs becomes more difficult and costs moretime and resources. Today functional verification capability lags behind designcapability significantly. The functional verification became a bottleneck of large-scalechips design. There is several new verification techniques which came out in recentyears, for example, assertion based verifiction, functional coverage, constraintramdom stimulus and etc, but the new meliorate trend of verifiction is to establish amore structural and more systemic verification flow.CDV (Coverage Driven Verification) is a new verification methology, which canimprove the efficiency obviously. It has been proved to be a advanced verificationmethod in real world industrial IC design. And almost every EDA company hasfocused on the Coverage drive verification. So it may become a major verificationmethology in a few years.This dissertation gives a detail reserch with CDV, summerizes the wholeverification environment and every component of CDV, and then focus on how tobuild a CDV verificaton environment. By discussing the structure of testbench,functional coverage model building, and the stimulus generation and the reponsechecking of CDV, the dissertation compares the difference of CDV and otherverification methology and intruduces many detail of the design flow of buildingCDV environment. There is also some new techniques and its application in thisdissertation, for example, assertion based verification. The author established theCDV environment for 64 bit CPU design using HVL (Hardware VerificationLanguage). A few experimentation is also presented in this dissertation.