Research On Inter-communication For Multi-core Processors

With the continuous advancement of processor manufacturing process as well as the exposed limination of single-core processors, multi-core processors has become the inevitable outcome of the practical application needs and technological development. With the emergence of multi-core processors, some problems were brought. One of the hot issues is communication tecnology between multi-core processors in computer architecture today.Nowadays, there are two popular kinds of communication structure between multi-core processors:one is the cache structure based on the shared bus, represented by the hydra multi-core processors developed by Stanford University. This structure is suitable for homogeneous multi-core processors. The other one is on-chip interconnect structure, represented by RAW multi-core processors developed by Massachusetts Institute of Technology. This structure is suiatable for heterogeneous multi-core processors.The developing situation of inter-core communication, the introduction of multi-core processor and the classification of multi-core processor were firstly introduced in this paper. After based on the deep study of the concept of process, the working principle of inter-process communication and three main communtion ways, aiming at advantages and disadvantages of the existing two communication structure, presents a task classification based communication model of multi-core processors which complete the communication through shared memory. This model divides the tasks running on the CPU into computing tasks and control tasks. At the same time multi-core are divided into computing cores and control cores. The function of control cores are mainly for handling applications on the Server, controling the computer system and I/O access. The function of computing cores are mainly for computing and processing large amounts of data, for example multimedia data processing, data processing in database, scientific computing and so on. By the affinity of kernel, the I/O part of the application will be sent to run on control cores and the computing part will be sent to run on computing cores in parallel. Meanwhile, according to the different demands of communication between multi-core processors, this paper presents three different communication channels, including communication among cores, control cores and I/O device communication and computing cores and I/O device communication.Finally, the system was tested by the software of multi-core simulator GEMS. Experimental results show that the task-based communication model presented in this paper reduces the communication delay and increases the performance of muti-core processors.